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Posts Tagged ‘Synopsys’

Sonics: IP Pricing and Protocols

Thursday, February 27th, 2014

 

It makes it worthwhile to show up for work on days when you get to have a conversation with people like the folks of Sonics, a System IP vendor based in Silicon Valley. Articulate and knowledgeable, they have a nuanced understanding of how the IP business works, its challenges and opportunities.

When I spoke to them last week about my ongoing project to assemble IP for the chip in my Dick Tracy keychain, President & CEO Grant Pierce and VP of Operations Raymond Brinks were both on the call. We started by talking about how IP is priced.

Per Pierce: “The conditions under which various customers buy and use IP can be quite different. We have some customers who are fairly sophisticated. We sell [such customers] licensed IP, offer some initial training, and then off they go. After that, apart from an occasional email, we have little contact with them. There are customers, however, who are opposite in the extreme.

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2013_Q3: The Good Times continue, with qualification

Wednesday, January 15th, 2014

 

It’s clear that these are heady days in EDA and IP. The numbers have been up and to the right for a number of quarters now and everybody’s feeling good about things, including Mentor Graphics CEO Wally Rhines. He was doing the rounds last week talking up EDAC’s Market Statistics Service report on the industry for Q3_2013; the report was published this week on Tuesday.

On my phone call with Rhines I found him exuberant, so I started with a comment to which Rhines was not allowed to respond; he was speaking for EDAC in that conversation and not for his own organization.  “Wow,” I said. “Mentor is really doing stupendously if your stock valuations are any indication, up over 40 percent in the last year.”

Rhines said nothing, but did chuckle, so I continued: “Wow again, then, for the overall EDA and IP industries. Having said that, I’ve noticed – perhaps not for the first time – that Synopsys does not officially submit numbers for these quarterly MSS updates. What’s up with that?”

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CES 2014: why was Cadence there?

Thursday, January 9th, 2014

 

Since the ginormous Consumer Electronics Show in Las Vegas this week is widely touted as the biggest event since the invention of humankind, it’s hard to admit two things: a) I wasn’t there, and yet b) I’ve been asked to compose a blog about it. Somewhat of a challenge, but not an insurmountable one.

To attend to the task at hand, I slogged through the blogosphere to see what people who were there this week had to say about it all, after knocking in and around the largest conference on the planet.

Turns out their take-aways are pretty consistent: Among the 3000+ exhibitors, there were more toys on display than you could play with in a month of Sundays, drones are everywhere and somewhat creepy, TVs are getting bigger, electric cars are getting more so, everything’s wearable, and the only things left that are truly private and un-recordable in the mania of this digital age are your thoughts, and those are probably under assault in an evil lab somewhere. [Note to self: don’t sell them for a penny.]

Another way to approach CES, if you blog about EDA and IP, is to go to the roster of EDAC and see who on that list was exhibiting this week in Las Vegas. The results are rather surprising – only ARM and Cadence.

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2013: to Infinity & Beyond …

Thursday, December 19th, 2013

 

This has been a complex year. Some stories were ferocious: the unspeakable double punch of earthquake and typhoon in the Philippines; the ongoing civil war in Syria; the Snowden/NSA revelations; the military coup in Egypt; the Boston Marathon bombings; the shopping mall attack in Nairobi; the shootings at the Washington Navy Yard; the discovery of kidnapping victims in Cleveland. Some stories were about historic change: a new pope; the death of Nelson Mandela; a choppy roll-out for the Affordable Healthcare Act.

Some stories were about trends: a decrease in unemployment; an increase in the financial markets; a marked uptick in housing values; the majority now carrying smart phones. Some stories were about SIP: Synopsys let loose a slew of IP-related press releases; Cadence acquired Tensilica and did the same; TSMC continued to portray itself as a foundry that just happens to have 3000+ IP cores in its arsenal; ARM remained the 800-pound gorilla.

Some stories were about EDA: Mentor talked non-stop about customers in the transportation sector and out-performed the Nasdaq, Dow, S&P500, CDNS and SNPS. FinFETs were all the rage, players big and small declared their readiness to embrace the technology, and Berkeley Prof. Chenming Hu accepted the Phil Kaufman Award. DAC celebrated 50 years and moved to Austin. EDAC had a party, celebrated EDA’s golden anniversary, and helped prepare a place of honor for design automation in the Computer History Museum. The industry sent a collective shout-out to Gary Smith.

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IP Sampler: Self-evident truths

Thursday, October 17th, 2013

 

A brief sampler of recent announcements on the IP front reveal distinct themes in the marketplace. IP development and integration require a viable ecosystem of suppliers and tool vendors; automotive, audio and mobile apps continue to be important targets for IP developers whose customers seek better safety, longer battery life, and truer sound (particularly for sporting events and concerts of aging rockers); IP interfaces remain crucial; and platform-based design totally depends on further enhancements in IP technologies.

Additionally, acquisitions definitely pan out for the companies smart enough to snap up the good ones: Synopsys/ARC, Cadence/Tensilica, and Imagination/MIPS.

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EDAC Seminar: EDA & Export Compliance

Thursday, September 26th, 2013

 

EDAC hosted an evening seminar last week that could have taught you everything your company needs to know to meet your Export Compliance requirements – an unbelievably labyrinthine set of rules, created and nurtured by various agencies of the U.S. Government, that are designed in part to prevent sensitive technical IP from falling into the hands of less-than-totally-friendly nation states.

If you weren’t there on September 18th, you were not alone. A surprisingly small number of people showed up for the seminar, although the speaker, Cadence Group Director for Export Compliance and Government Relations Larry Disenhof, is clearly a walking encyclopedia on this stuff, and although EDAC did a great job publicizing the event.

If you didn’t attend EDA & Export Compliance, it was probably for one of two reasons:  Your team already knows everything they need to know in order to meet their export obligations, or your team is oblivious to the fact that these requirements are not optional; they’re obligatory and failure to comply can precipitate fines of $250,000 and up, loss of export privileges, cancellation of pending M&A’s, and even jail time.

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SNPS Sensor Subsystem: far-reaching implications

Thursday, August 15th, 2013

 

Late last month, Synopsys announced another important addition to their portfolio, the DesignWare Sensor IP Subsystem. Per the company, “The new IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.

“The hardware components [include] a power- and area-efficient DesignWare 32-bit ARC EM4 processor, digital peripherals such as I2C, SPI, ADC interface, and GPIO, and hardware accelerators for signal processing functions. The software components [include] a comprehensive library of digital signal functions utilized in higher-level applications such as analog and digital sensor fusion, and mathematical functions, filtering and interpolation. In addition, peripheral drivers ease integration of the I/O with the ARC EM processor.”

With announcements such as this, two questions come to mind: Why are companies like Synopsys still classified as EDA with some IP, and not IP with some EDA? And isn’t Synopsys setting itself up as competition for its customers by selling such a sophisticated chunk of IP?

I had a chance to speak by phone last week with Rich Collins, Marketing Manager for Synopsys’ IP Subsystems, who answered my second question with ease: “I don’t think so, because this [subsystem] is not a critical part of the SoC. Our customers are trying to achieve a higher order of functionality. It’s our value proposition that by using this subsystem, we save them months and months of design and verification effort. We help them get to market more quickly, we are not in competition with them.”

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Future of IP: from Tensilica to IPextreme

Thursday, August 1st, 2013

 

Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.

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Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.

At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.

Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:

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Update: IP on the move

Thursday, June 20th, 2013

 

Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.


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Synopsys and OCZ Technology Group announced OCZ “achieved first-pass silicon success” in its newest NAND flash Vector SSD using Synopsys’ DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System, and Professional Services.

The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”

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DAC 2013: IP news in advance of Austin

Thursday, May 30th, 2013

 

** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits.

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