Posts Tagged ‘Synopsys’
Thursday, September 26th, 2013
EDAC hosted an evening seminar last week that could have taught you everything your company needs to know to meet your Export Compliance requirements – an unbelievably labyrinthine set of rules, created and nurtured by various agencies of the U.S. Government, that are designed in part to prevent sensitive technical IP from falling into the hands of less-than-totally-friendly nation states.
If you weren’t there on September 18th, you were not alone. A surprisingly small number of people showed up for the seminar, although the speaker, Cadence Group Director for Export Compliance and Government Relations Larry Disenhof, is clearly a walking encyclopedia on this stuff, and although EDAC did a great job publicizing the event.
If you didn’t attend EDA & Export Compliance, it was probably for one of two reasons: Your team already knows everything they need to know in order to meet their export obligations, or your team is oblivious to the fact that these requirements are not optional; they’re obligatory and failure to comply can precipitate fines of $250,000 and up, loss of export privileges, cancellation of pending M&A’s, and even jail time.
Thursday, August 15th, 2013
Late last month, Synopsys announced another important addition to their portfolio, the DesignWare Sensor IP Subsystem. Per the company, “The new IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.
“The hardware components [include] a power- and area-efficient DesignWare 32-bit ARC EM4 processor, digital peripherals such as I2C, SPI, ADC interface, and GPIO, and hardware accelerators for signal processing functions. The software components [include] a comprehensive library of digital signal functions utilized in higher-level applications such as analog and digital sensor fusion, and mathematical functions, filtering and interpolation. In addition, peripheral drivers ease integration of the I/O with the ARC EM processor.”
With announcements such as this, two questions come to mind: Why are companies like Synopsys still classified as EDA with some IP, and not IP with some EDA? And isn’t Synopsys setting itself up as competition for its customers by selling such a sophisticated chunk of IP?
I had a chance to speak by phone last week with Rich Collins, Marketing Manager for Synopsys’ IP Subsystems, who answered my second question with ease: “I don’t think so, because this [subsystem] is not a critical part of the SoC. Our customers are trying to achieve a higher order of functionality. It’s our value proposition that by using this subsystem, we save them months and months of design and verification effort. We help them get to market more quickly, we are not in competition with them.”
Thursday, August 1st, 2013
Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.
Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.
At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.
Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:
Thursday, June 20th, 2013
Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.
** Synopsys and OCZ Technology Group announced OCZ “achieved first-pass silicon success” in its newest NAND flash Vector SSD using Synopsys’ DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System, and Professional Services.
The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”
Thursday, May 30th, 2013
** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits.
Thursday, April 4th, 2013
Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars.
Here’s your DAC planning guide …
Thursday, March 21st, 2013
If you thought about going to the Synopsys Users Group meeting next week in Silicon Valley, there’s at least one topic that would make it worth your time: This week ARM and Synopsys announced “optimized 28-nm Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters, as well as the CoreLink CCI-400 cache-coherent interconnect.”
The reference implementations are currently available, and include “scripts, floorplan, constraints and documentation” – scripts that are built on Synopsys’ tool Reference Methodologies and are optimized for high-performance cores. Clearly attending SNUG would clarify what you need to know to use all of this, but first apparently you need to understand ARM’s big.LITTLE processing. Which is what?
Tuesday, March 12th, 2013
As the trading day in New York draws to a close, it would appear that some analysts are correct; the market’s not too pleased about yesterday’s announcement that Cadence is acquiring Tensilica. Shares of CDNS are trading down well over 3% today. But you know, the market’s stupid. They understand zip zero nada about EDA or IP, and really why should they?
After all, EDA and IP providers make the black magic that they do look so easy. And, they’re constantly telling people that what they do isn’t rocket science. But it is! The EDA vendors make the tools that IP vendors use to create their products, and designers use to integrate said IP into the larger designs. It’s called an eco-system and it is rocket science.
It’s also on the level of brain surgery, quantum physics, and a bunch of other esoteric science and engineering disciplines that require a lot of education and and a lot of OJT, and even then is really hard to do. How many traders on Wall Street, or the analysts who track it all, really understand what EDA and/or IP are all about? Exactly!
Thursday, February 28th, 2013
If you’re free on the evening of Thursday, March 14th, you should plan on attending EDAC’s annual CEO Forecast Panel. It promises to be full of executive content, albeit perhaps a bit light on forecast content, but oh well. That’s the nature of life in the Publicly Traded Fast Lane these days.
Along with the CEOs of Mentor Graphics, Cadence, Synopsys, and Nimbic, the president of ARM will also be on stage, Simon Segars. Segars is no stranger to public speaking. You can hear his recent ARM TechCon 2012 keynote here. But it’s not what Segars will say on stage at the DoubleTree Hotel in San Jose on March 14th that matters. It’s his body language, and you’ll only be able to read that if you’re in the room.
Thursday, February 14th, 2013
After the euphoniously monikered IP provider, Uniquify, announced several weeks ago that the more whimsically monikered organization, Pixelworks, is using Uniquify’s DDR memory controller subsystem IP for multiple distinct processors that Pixelworks is, in turn, providing to TV makers who make 4Kx2K ultra high-def systems, one question still remained: How did Pixelworks know to use Uniquify’s offering?
According to a January 2013 article in IEEE Spectrum, knowing what IP to use in a project here in the 21st century is fairly easy knowledge to come by. I don’t know what planet the author of the op-ed piece, “Other People’s Knowledge”, lives on but it doesn’t seem to be the one that I hear about from the folks who make or buy third-party IP.
In fact, those people seem to indicate that knowing what IP to use in a particular project continues to be far more art than science. In particular, because until a system, or sub-system, is fully defined, modeled and simulated – let alone, manufactured and deployed in the field – one can never really know how a piece of IP is going to work in the environment into which it’s been placed.