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Posts Tagged ‘Synopsys’

ESD Alliance: Sonics’ Grant Pierce elected Board Chair

Thursday, February 9th, 2017

 


This week, the ESD Alliance
announced that Sonics CEO Grant Pierce has been elected chair of the organization’s Board of Directors. His election is unique in several ways: Pierce is the first CEO of an IP company to lead the Alliance; he replaces two co-chairs, Cadence CEO Lip-Bu Tan and PDF Solutions, John Kibarian; and he is only the second CEO of a non-publicly traded company to serve as Board Chair, the other being Jasper CEO Kathryn Kranen who took the reins in 2012.

When Pierce and I spoke by phone on Tuesday about his election, he noted the unique circumstances of his new leadership role: “When I joined the board several years ago, it was with the intention to add a new point of view to what was then the EDA Consortium, to help the organization reflect the emerging reality of what was happening in the marketplace with respect to IP companies.

“In some ways, the IP companies consider themselves to be a necessary evil. Every chip developed today involves some sort of third-party IP, so having a place on the Board of the ESD Alliance is essential.”

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DAC 2017: Deadlines for IP Submissions start November 15th

Thursday, November 10th, 2016

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

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EDA Death Spiral: Qualcomm/NXP last nail in coffin

Thursday, October 27th, 2016

 


Raise your hand if you think innovation comes out of small, nimble, edgy startups
. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.

Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.

Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.

However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.

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DVCon Munich: IP Integration, Automotive, Smart Cities, System Design

Thursday, October 13th, 2016

 


Next week, DVCon is once again in Europe, October 19-20 in Munich
. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.

It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.

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The Tate Effect: Confidence in Flex Logix Team & Technology

Thursday, September 22nd, 2016

 


Geoff Tate, founding CEO at Rambus, is busy – again.
 These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.

When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.

“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”

“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”

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IP Theft: Cheaters & Chuckles vs. Chalk & Cheese

Thursday, September 15th, 2016

 


Synopsys has a problem.
Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.

Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.

Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.

In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.

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Mac on DAC: IP is critical, and so is everything else

Thursday, May 12th, 2016

 


IP will be well represented at DAC
 according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.

Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.

A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]

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SNPS’ Custom Compiler: closing the FinFET productivity gap

Thursday, April 7th, 2016

 


Synopsys Marketing Director and long-time EDA contributor Dave Reed
 talked recently about the company’s new, highly anticipated product release, Custom Compiler.

“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”

Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”

There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.

“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.

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Emulation: DVCon invites Rizzatti to Expound

Thursday, February 18th, 2016

 


The folks at DVCon have done a brilliant thing.
They’ve invited Lauro Rizzatti to present at their upcoming conference on a topic that Rizzatti knows better than anybody, emulation. Last year alone, he wrote 40 articles on the subject.

More importantly, of course, Rizzatti helped guide EVE, the high-flying European EDA company that led the field in emulation from their base in France before being acquired by Synopsys in 2012. I spoke with Rizzatti this week about emulation, his talk at DVCon, and his recent endeavors writing about a technology that’s taking the world of verification by storm.

He started by establishing the importance of emulation today: “This technology is here to stay. It’s been around for 30 years, and [historically] was something only the big companies could afford to buy and use. They needed an army of engineers. Today it’s no longer a niche technology, however; it’s mainstream.”

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SmartFlow Compliance Solutions: Taking the offensive on Software Piracy

Wednesday, November 18th, 2015

 


This week Synopsys announced “unauthorized third-party access to Synopsys EDA, IP and optical products
and product license files through its customer-facing license and product delivery system. The unauthorized access, which began in July 2015, was discovered by Synopsys in October 2015.”

The fact that the company needs to make this announcement is indicative of a new attitude towards an old problem: Software companies who lose their products to theft and piracy no longer want to just buck up and get past it, particularly in EDA. Instead, they want tools and strategies to go after their adversaries. The newly launched startup SmartFlow Compliance Solutions, just announced last week, is planning to offer such tools.

Launched by Ted Miracco – one of the founders of EDA vendor AWR Corp. – SmartFlow is based on his experience dealing with pirated AWR product software, including tracking down and forcing restitution from companies who were proven culpable. In a phone call last week discussing his new company, Miracco said pirated software is more than just an occasional nuisance, it’s resulting in billions of dollars in lost revenue to the companies whose products are being used without licenses.

More profound than lost profits, however, is the ’tilting’ of the playing field. When companies who use pirated software to design chips or systems are able to undercut their competition by underpaying for the tools they need, or by not paying at all, the competition is hobbled.

In response, SmartFlow has engineered a complex set of tools and protocols that will allow companies to unearth pirated instantiations of their software across a variety of customer profiles. To begin their effort to build those tools, Miracco and his team looked closely at software non-compliance around the globe, parsed the different types of pirates and examined their principal strategies.

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CST: Webinar series



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