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Posts Tagged ‘SNUG’

DAC 2017: Deadlines for IP Submissions start November 15th

Thursday, November 10th, 2016

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

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SNUG: Lunch with a proper stranger

Thursday, March 28th, 2013

 

The best part of attending a conference like SNUG is plunging into a room of hundreds of anonymous lunch munchers and striking up a conversation with a stranger. Over the course of the meal, you’ll learn a little bit about somebody’s career, their expertise, and their concerns.

This week’s networking lunch at the Santa Clara Convention Center was no different. I had a chance to converse for 30 minutes with a lunch companion at a table full of strangers. By the end of the meal, I had heard first-hand about a really big problem for small IP vendors attempting to succeed in the current market – they can’t. According to my lunch companion, it’s nigh-on impossible to compete against ARM.

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ARM & SNPS: implementing big.LITTLE

Thursday, March 21st, 2013

 

If you thought about going to the Synopsys Users Group meeting next week in Silicon Valley, there’s at least one topic that would make it worth your time: This week ARM and Synopsys announced “optimized 28-nm Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters, as well as the CoreLink CCI-400 cache-coherent interconnect.”

The reference implementations are currently available, and include “scripts, floorplan, constraints and documentation” – scripts that are built on Synopsys’ tool Reference Methodologies and are optimized for high-performance cores. Clearly attending SNUG would clarify what you need to know to use all of this, but first apparently you need to understand ARM’s big.LITTLE processing. Which is what?

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CST: Webinar series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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