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SNPS Sensor Subsystem: far-reaching implications

Thursday, August 15th, 2013

 

Late last month, Synopsys announced another important addition to their portfolio, the DesignWare Sensor IP Subsystem. Per the company, “The new IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.

“The hardware components [include] a power- and area-efficient DesignWare 32-bit ARC EM4 processor, digital peripherals such as I2C, SPI, ADC interface, and GPIO, and hardware accelerators for signal processing functions. The software components [include] a comprehensive library of digital signal functions utilized in higher-level applications such as analog and digital sensor fusion, and mathematical functions, filtering and interpolation. In addition, peripheral drivers ease integration of the I/O with the ARC EM processor.”

With announcements such as this, two questions come to mind: Why are companies like Synopsys still classified as EDA with some IP, and not IP with some EDA? And isn’t Synopsys setting itself up as competition for its customers by selling such a sophisticated chunk of IP?

I had a chance to speak by phone last week with Rich Collins, Marketing Manager for Synopsys’ IP Subsystems, who answered my second question with ease: “I don’t think so, because this [subsystem] is not a critical part of the SoC. Our customers are trying to achieve a higher order of functionality. It’s our value proposition that by using this subsystem, we save them months and months of design and verification effort. We help them get to market more quickly, we are not in competition with them.”

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