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Posts Tagged ‘ESD Alliance’

DVCon Munich: IP Integration, Automotive, Smart Cities, System Design

Thursday, October 13th, 2016


Next week, DVCon is once again in Europe, October 19-20 in Munich
. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.

It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.


IP Theft: Cheaters & Chuckles vs. Chalk & Cheese

Thursday, September 15th, 2016


Synopsys has a problem.
Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.

Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.

Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.

In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.


ESD Alliance: New members bring opportunities, concerns

Thursday, September 8th, 2016


Over the last several weeks, the ESD Alliance has announced
two more members, news of particular interest because both companies are IP vendors. C-Sky Microsystems provides 32-bit embedded CPU cores, and Silvaco provides EDA tools for development of analog/mixed-signal devices, power IC and memory design.

True, Silvaco doesn’t sound like an IP vendor until you remember that it just acquired IPextreme, a well-known player in the IP market headed up by Warren Savage. And Savage, now GM of Silvaco’s IP Division, has recently been named chair of the ESD Alliance Semiconductor IP Working Group, tasked with developing a common methodology, best practices for fingerprinting, and solutions for tracking and auditing IP.

Meanwhile, C-Sky Microsystems brings its own unique value proposition to ESD Alliance. Described in the Press Release as “the first IP company from China to join the ESD Alliance,” C-Sky says it intends to actively participate in Savages’ SIP Working Group. This second bit is admirable, but the first could prove complicated.


IP Panel: What keeps you awake at night?

Thursday, August 11th, 2016


It’s fantastic to see that the ESD Alliance is following through
with its new-found commitment to promote discussion about the IP industry. On Wednesday, September 14th, the Alliance is hosting an evening panel at their headquarters in Santa Clara to discuss semiconductor IP issues that “Keep You Awake at Night”.

As background, consider that the massive amounts of IP involved in building a modern SoC may translate into IP vendors losing millions of dollars if their IP is used therein without proper licensing. At the same time, semiconductor companies also wrestle with troubling issues if their engineers accidentally reuse a core without proper licensing, possibly exposing their employers to huge liabilities. The ESD Alliance event in September promises to address these thorny problems.

Moderated by industry leader Warren Savage – formerly CEO of IPextreme, but now GM of IP at Silvaco with the acquisition announced just prior to DAC – the evening’s two panelists come from interesting backgrounds.


Kapow Wham Boom: Holy Acquisition, Sir Robin!

Monday, July 18th, 2016

Yep, it’s happened
. More astonishing than Brexit. Faster than a skyrocketing market cap. Stronger than any ties to Merry Old England, Apple, or ESDA. Able to leap over continents in a single bound.

Holy All-Cash-Deal, Sir Robin, ARM’s been bought by SoftBank!

For a mere 24.3 billion pounds.


Please Crispify: The ESD Alliance System Scaling Working Group

Thursday, May 19th, 2016


It’s a poorly kept secret that Bob Smith
was brought in as Executive Director of EDAC last year to shake things up, to breathe new life into the sails of a somewhat becalmed organization. Well, in the category of be careful what you ask for, here’s how things have gone so far:

New companies have joined the consortium, the newest member of the Board of Directors is not a CEO, a plethora of monthly panels have engaged the industry in thought-provoking discussions about innovation vis-à-vis commercial enterprise, a marketing deal has been struck with Semico, and the whole friggin’ organization has been re-branded as the ESD Alliance to reflect an intent to get more IP guys, more Embedded guys, and more Yet-to-be-identified guys into the alliance than just the traditional anchor tenants from EDA.

But none of this comes close to the potential impact of the latest disruptive idea that ESDA is proposing: The founding of a brand new working group that could very well redefine the whole semiconductor supply chain: The ESD Alliance System Scaling Working Group.



Warren Savage: Optimism for IP at DAC and beyond

Thursday, May 5th, 2016


Warren Savage, CEO at IPextreme, is willing to address questions regarding IP content at DAC 2016
, enthusiastic in fact. That’s not surprising, given that he serves on the IP Track Committee that reviews the content.

“I think the content’s very good this year,” Savage said in a recent phone call. “We’ve been working on the IP content at the DAC for 3 years, and continue to make progress. I would say the biggest thing [we struggle with] is insufficient time allocated for IP.

“In comparison to previous years, however, the IP and Design tracks have been merged and all put under the same track – something we recommended against, because design-related submissions generally are different from IP-related submissions.”


ESD Alliance: Lanza and Semico to serve as Change Agents

Wednesday, April 20th, 2016


The ESD Alliance has announced two additional updates
on its remarkable road to renaissance. The Alliance formerly known as the EDA Consortium says Dr. Lucio Lanza, long-time EDA investor and 2014 Kaufman Award winner, is joining the organization’s board of directors, effective immediately.

That news is unique for 4 reasons: a) Lanza is the first new board member since EDAC was relaunched as ESDA; b) Lanza is the only member of the board who is not currently serving as the CEO of a company, the first such circumstance in recent memory; c) Lanza serves on the board of PDF Solutions, triggering another first in that one company is now represented twice on the EDAC/ESDA board with PDF’s John Kibarian also serving therein; and d) Lanza was not elected, but appointed.

Certainly for all of these reasons and more, Dr. Lucio Lanza will serve as a refreshing change agent as the EDA Consortium morphs into the ESD Alliance.

The second major update from the ESD Alliance is the announcement of a “cooperative marketing” partnership with Semico.


IP @ DAC: Sound & Fury or Smoke & Mirrors

Thursday, April 14th, 2016


IP now dominates design automation
, evidenced in no small measure by ARM’s seat at the head of the table for the ESD Alliance, ESDA being an important sponsor of the Design Automation Conference. Everyone seems to agree that IP reuse is the only way complex mega-systems of the 21st century can be designed, so not surprisingly the DAC program now reflects that reality. There are sessions every day categorized as being IP-related, but are those designations accurate?

I would argue that a lot of the content that’s sitting in the IP Track at DAC is really just about design, and not specifically about IP-based design. To prove that point, below is a complete listing of the sessions in the IP Track that’s set to air between June 6th and 9th at DAC in Austin. Those that are legitimately about IP are bolded, sessions that actually talk about using IP. Those not bolded are ‘just’ about design, or are merely high-level nattering about superficial issues associated with IP reuse.

Conclusion: the number of IP-related sessions are far fewer than one would hope. If IP is this important, why aren’t there more sessions that are really about IP? Is there a conspiracy here?

Fortunately, this next week I’m talking at length with Warren Savage. As CEO of IPextreme, his knowledge about the technology and business of IP is pretty encyclopedic. I will run my conspiracy theory past him: DAC wants you to believe they believe in IP, but in fact the conference is still more about design automation, not about using silicon IP to enhance the process. EDA vendors still rule the roost at DAC.


Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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