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Posts Tagged ‘Ed Sperling’

ESDA CEO Confab: It was a Dark and Stormy Night

Thursday, April 13th, 2017

 


Something eerie and inexplicable happened on Thursday evening, April 6th
. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.

Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.

Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.

No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.

That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.

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IP @ DAC: Design reuse still not for faint of heart

Thursday, April 16th, 2015

 

Building on last year’s success, the 2015 Design Automation Conference in San Francisco is offering even more substantial content in the track centered on silicon IP and design reuse. Reading through the list of topics, speakers, and companies set to be featured across a diverse set of sessions from June 7-9 at Moscone Center, two things are obvious.

One, a lot of work has been done to assemble all of this. And two, it’s possible the thorny issues surrounding IP reuse may never go away: integration, verifying quality, convincing staff to use design blocks that originate outside of the group, and dealing with the massive amounts of data that IP selection and reuse generates.

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2013: to Infinity & Beyond …

Thursday, December 19th, 2013

 

This has been a complex year. Some stories were ferocious: the unspeakable double punch of earthquake and typhoon in the Philippines; the ongoing civil war in Syria; the Snowden/NSA revelations; the military coup in Egypt; the Boston Marathon bombings; the shopping mall attack in Nairobi; the shootings at the Washington Navy Yard; the discovery of kidnapping victims in Cleveland. Some stories were about historic change: a new pope; the death of Nelson Mandela; a choppy roll-out for the Affordable Healthcare Act.

Some stories were about trends: a decrease in unemployment; an increase in the financial markets; a marked uptick in housing values; the majority now carrying smart phones. Some stories were about SIP: Synopsys let loose a slew of IP-related press releases; Cadence acquired Tensilica and did the same; TSMC continued to portray itself as a foundry that just happens to have 3000+ IP cores in its arsenal; ARM remained the 800-pound gorilla.

Some stories were about EDA: Mentor talked non-stop about customers in the transportation sector and out-performed the Nasdaq, Dow, S&P500, CDNS and SNPS. FinFETs were all the rage, players big and small declared their readiness to embrace the technology, and Berkeley Prof. Chenming Hu accepted the Phil Kaufman Award. DAC celebrated 50 years and moved to Austin. EDAC had a party, celebrated EDA’s golden anniversary, and helped prepare a place of honor for design automation in the Computer History Museum. The industry sent a collective shout-out to Gary Smith.

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CST: Webinar series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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