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SNPS’ Custom Compiler: closing the FinFET productivity gap

Thursday, April 7th, 2016


Synopsys Marketing Director and long-time EDA contributor Dave Reed
 talked recently about the company’s new, highly anticipated product release, Custom Compiler.

“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”

Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”

There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.

“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.


S2C: FPGA Base prototyping- Download white paper

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