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Posts Tagged ‘Chris Rowen’

Future of IP: from Tensilica to IPextreme

Thursday, August 1st, 2013

 

Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.

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Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.

At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.

Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:

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IP @ DAC: a session a day keeps the doctor away

Thursday, April 4th, 2013

 

Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars.

Here’s your DAC planning guide …

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M&A: CDNS + Tensilica = win/win

Tuesday, March 12th, 2013

 

As the trading day in New York draws to a close, it would appear that some analysts are correct; the market’s not too pleased about yesterday’s announcement that Cadence is acquiring Tensilica. Shares of CDNS are trading down well over 3% today. But you know, the market’s stupid. They understand zip zero nada about EDA or IP, and really why should they?

After all, EDA and IP providers make the black magic that they do look so easy. And, they’re constantly telling people that what they do isn’t rocket science. But it is! The EDA vendors make the tools that IP vendors use to create their products, and designers use to integrate said IP into the larger designs. It’s called an eco-system and it is rocket science.

It’s also on the level of brain surgery, quantum physics, and a bunch of other esoteric science and engineering disciplines that require a lot of education and and a lot of OJT, and even then is really hard to do. How many traders on Wall Street, or the analysts who track it all, really understand what EDA and/or IP are all about? Exactly!

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Chris Rowen: Tensilica’s rational trajectory

Tuesday, September 18th, 2012

 

Chris Rowen is Founder and CTO of Tensilica, an IP company based in Silicon Valley. We spoke last week by phone to discuss how an IP company decides what and when to introduce new products.

I first asked to Chris for a brief history of the RISC [Reduced Instruction Set Computing] architecture he is closely associated with, and how that history segued into the founding of Tensilica.

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From RISC to Tensilica …

Q: Can you give me a quick overview of the origins of RISC architecture?

Chris Rowen: RISC is a set of ideas that grew up in academia and IBM in response to increased architectures in both the mainframe and microprocessor worlds.

People saw machines with really high hardware costs being built for assembly [language applications]. However, as compiler technology got better, people said: If I want a compiler to run well, I don’t need fancy instructions. I only need a common set of instructions that run really fast. All other complex operations could be composed by the compiler out of these fast, simple operations.

RISC grew out of these compiler technology advances, and a recognition in the VLSI era that there was an opportunity to rethink the process of how the architecture could be put together. (more…)

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