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Posts Tagged ‘Cadence’

UltraSoC: Sangiovanni-Vincentelli now leads Board

Thursday, November 2nd, 2017

 


U.C. Berkeley Prof. Alberto Sangiovanni-Vincentelli has just been named non-Executive Chairman of UltraSoC
, an IP provider based in Cambridge. He was in Rome when we spoke this week by phone about the news.

UltraSoC CEO Rupert Baines was also on the conference call, dialing in from the UK, while I was in Silicon Valley. The conversation began with a discussion of Sangiovanni-Vincentelli’s ongoing research work in Singapore.

Three sentences, four geographies: What more proof is needed that the semiconductor industry is indeed global?

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IC Manage: A Roadmap out to Forever

Thursday, September 7th, 2017

 


Talking to Dean Drako is probably a little like talking to Elon Musk:
Both men have their fingers in multiple pies. In Drako’s case, and apropos to semiconductor design, one pie includes the IP and EDA industries.

Dean Drako founded IC Manage in 2003, a company whose products are targeted at IC designers who need help coordinating their efforts, integrating third-party IP into their design equation, and accelerating design. Interestingly, at the same time Drako was founding IC Manage, he was also founding Barracuda Networks, and ran both companies simultaneously for a number of years.

Today 14 years later, Drako still serves as President and CEO of IC Manage, but is ‘only’ on the board of Barracuda. Lest you think his plate is not full enough, however, he’s also currently President and CEO of Eagle Eye Networks.

Prior to our phone call last week, I researched Drako on Wikipedia: “Drako has written a number of articles on Open Source, Big Data, and SoC design. He is a frequently invited speaker on the topic of entrepreneurship [and] is a holder of 27 patents, including patents in network security, network protocols, digital circuits, software, biochemical processes, and sporting equipment.”

Yeah, pretty much just like talking to Elon Musk.

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Hal Barbour: 8 Grand Challenges in IP

Thursday, May 25th, 2017

 


This conversation with Hal Barbour,
Chairman at CAST IP, is the second of four dialogs about Grand Challenges in IP.

The first installment in the series, published last week, was a conversation with Sonics co-Founder and CEO Grant Pierce.

Pierce argues that today’s Grand Challenges in IP center around the complexities of delivering sub-systems and related technical expertise to customers, helping develop edge-node devices targeted at Machine Learning, and providing IP for myriad automotive systems – all while meeting demands for greater bandwidth and throughput, and astonishingly low power.

In this week’s installment in the series, Hal Barbour talks about a completely different set of Grand Challenges in IP – those related to the business issues surrounding the industry.

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Celebrating Accellera’s UVM: Now it’s IEEE 1800.2

Thursday, April 27th, 2017

 


Tom Alsop and the team at Accellera are elated
: The UVM standard has been accepted by the IEEE as 1800.2 and congratulations are certainly in order.

The effort has consumed upwards of 10 years, and represents thousands of man-hours of effort, consultation, compromise, consensus building, rinse and repeat. Over and over until the final product was polished, presented and approved by the IEEE. Not an easy process by anybody’s estimation.

When we spoke by phone this week about the Accellera announcement, I asked Tom Alsop [Principal Engineer at Intel] how difficult the whole thing had actually been.

He chuckled slightly: “For us, it was fairly difficult.”

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ESDA CEO Confab: It was a Dark and Stormy Night

Thursday, April 13th, 2017

 


Something eerie and inexplicable happened on Thursday evening, April 6th
. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.

Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.

Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.

No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.

That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.

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Performance-IP: Finding a Different way to Compete

Thursday, March 16th, 2017

 


It takes skill and surgical precision
to launch and maintain a tech startup, especially today and extra-especially in a market as competitive as IP. Nonetheless, Massachusetts-based Performance-IP seems to have accomplished that feat.

It’s true, this is not the first IP company co-founded by Performance-IP CTO Gregg Recupero. In the early 1990’s, he helped to found VAutomation which developed IP for system-level verification [and was acquired by ARC in 2000].

In our phone call this week, I asked Recupero how a small IP company today can compete with the behemoth IP providers.

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Oski Technology: new VIP supports Formal Sign-off

Thursday, February 23rd, 2017


Oski Technology has added a new page to its playbook.
Now it’s not just a services company, it’s an IP company as well. This week, the company announced it’s Formal Verification IP Library targeted at those companies using ARM’s AMBA interface protocols.

When we spoke on the phone about the announcement, I asked Oski VP of Applications Engineering Roger Sabbagh why now for this product release. He said: “I personally have been working in Formal since the year 2000, back when I joined 0-In, and over the years I’ve learned that formal adoption grows slowly.

“Yet although there has never been a knee in the curve, we have seen some important developments in the industry. Synopsys developed PC Formal and Cadence bought Jasper, both indicating that Formal is catching on slowly but surely.”

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ESD Alliance: Sonics’ Grant Pierce elected Board Chair

Thursday, February 9th, 2017

 


This week, the ESD Alliance
announced that Sonics CEO Grant Pierce has been elected chair of the organization’s Board of Directors. His election is unique in several ways: Pierce is the first CEO of an IP company to lead the Alliance; he replaces two co-chairs, Cadence CEO Lip-Bu Tan and PDF Solutions, John Kibarian; and he is only the second CEO of a non-publicly traded company to serve as Board Chair, the other being Jasper CEO Kathryn Kranen who took the reins in 2012.

When Pierce and I spoke by phone on Tuesday about his election, he noted the unique circumstances of his new leadership role: “When I joined the board several years ago, it was with the intention to add a new point of view to what was then the EDA Consortium, to help the organization reflect the emerging reality of what was happening in the marketplace with respect to IP companies.

“In some ways, the IP companies consider themselves to be a necessary evil. Every chip developed today involves some sort of third-party IP, so having a place on the Board of the ESD Alliance is essential.”

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DAC 2017: Deadlines for IP Submissions start November 15th

Thursday, November 10th, 2016

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

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EDA Death Spiral: Qualcomm/NXP last nail in coffin

Thursday, October 27th, 2016

 


Raise your hand if you think innovation comes out of small, nimble, edgy startups
. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.

Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.

Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.

However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.

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