Posts Tagged ‘Cadence’
Thursday, November 10th, 2016
Next Tuesday, November 15th, is the deadline for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.
[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]
In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.
The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.
Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.
So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?
Thursday, October 27th, 2016
Raise your hand if you think innovation comes out of small, nimble, edgy startups. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.
Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.
Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.
However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.
Thursday, October 13th, 2016
Next week, DVCon is once again in Europe, October 19-20 in Munich. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.
It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.
Thursday, September 22nd, 2016
Geoff Tate, founding CEO at Rambus, is busy – again. These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.
When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.
“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”
“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”
Thursday, June 23rd, 2016
At this writing, midnight is approaching here in California, it’s June 23rd, and highly anticipated news is arriving out of the UK. It’s Friday morning there and the results of the Should I stay or Should I go referendum have been announced. To the astonishment of some subset of the world, and undoubtedly their stock markets, the UK is leaving the European Union.
And so a page turns, another chapter begins, and now there’s a twist in the plot line that few saw coming. Although it’s a dark and starry night here, the sun is up in the UK and the future looks suddenly different, no matter if you’re standing on the streets of London, York, Edinburgh – or Cambridge.
The very same Cambridge where ARM Ltd. is headquartered.
Thursday, June 9th, 2016
When SRC’s Bill Joyner took the podium this past Sunday evening at the 53rd DAC in Austin, he did something that’s never been done before: Present a panel about careers that wasn’t part of a Workshop for Women in EDA.
Up until 7 o’clock on June 5, 2016, a conversation about career perspectives was such a non-technical topic, it could only be found in Marie Pistilli’s beloved workshop, a venue where work/life balance, Academia vs. Industry, and how to promote your brand within the organization were thoroughly discussed every year for 15 years at DAC.
Now IEEE’s Council on EDA, CEDA, has made the bold decision to pick up where Marie’s workshop left off, sponsoring this week’s event and broadening the audience and the appeal.
Joyner had four people on his panel, a generous two hours to hash out various universal questions, and enough of a sense of humor to offer to wear the necktie he’d brought with him to add gravitas, or not to wear the tie to appear hipster and cool. He quickly decided to go without the tie, and the ensuing conversation went something like this.
Thursday, February 18th, 2016
The folks at DVCon have done a brilliant thing. They’ve invited Lauro Rizzatti to present at their upcoming conference on a topic that Rizzatti knows better than anybody, emulation. Last year alone, he wrote 40 articles on the subject.
More importantly, of course, Rizzatti helped guide EVE, the high-flying European EDA company that led the field in emulation from their base in France before being acquired by Synopsys in 2012. I spoke with Rizzatti this week about emulation, his talk at DVCon, and his recent endeavors writing about a technology that’s taking the world of verification by storm.
He started by establishing the importance of emulation today: “This technology is here to stay. It’s been around for 30 years, and [historically] was something only the big companies could afford to buy and use. They needed an army of engineers. Today it’s no longer a niche technology, however; it’s mainstream.”
Wednesday, November 18th, 2015
This week Synopsys announced “unauthorized third-party access to Synopsys EDA, IP and optical products and product license files through its customer-facing license and product delivery system. The unauthorized access, which began in July 2015, was discovered by Synopsys in October 2015.”
The fact that the company needs to make this announcement is indicative of a new attitude towards an old problem: Software companies who lose their products to theft and piracy no longer want to just buck up and get past it, particularly in EDA. Instead, they want tools and strategies to go after their adversaries. The newly launched startup SmartFlow Compliance Solutions, just announced last week, is planning to offer such tools.
Launched by Ted Miracco – one of the founders of EDA vendor AWR Corp. – SmartFlow is based on his experience dealing with pirated AWR product software, including tracking down and forcing restitution from companies who were proven culpable. In a phone call last week discussing his new company, Miracco said pirated software is more than just an occasional nuisance, it’s resulting in billions of dollars in lost revenue to the companies whose products are being used without licenses.
More profound than lost profits, however, is the ’tilting’ of the playing field. When companies who use pirated software to design chips or systems are able to undercut their competition by underpaying for the tools they need, or by not paying at all, the competition is hobbled.
In response, SmartFlow has engineered a complex set of tools and protocols that will allow companies to unearth pirated instantiations of their software across a variety of customer profiles. To begin their effort to build those tools, Miracco and his team looked closely at software non-compliance around the globe, parsed the different types of pirates and examined their principal strategies.
Wednesday, September 9th, 2015
ARM must be doing something right when among the eight corporate sponsors for their upcoming Silicon Valley users conference in November, the top three companies in EDA are listed as Diamond or Platinum.
Cadence is Diamond, undoubtedly, because company President & CEO Lip-Bu Tan is co-chair of EDAC, and ARM CEO Simon Segars is on the EDAC Board. But why would Mentor and Synposys spend good money being Platinum sponsors of ARM’s show when they could put that particular chunk of disposable income into their own user conferences, or even DAC? Particularly since Mentor and Synopsys sell IP, as does Cadence, so in some ways the three EDA companies may actually be competing with ARM.
There are three possible answers: A) Mentor, Synopsys, and Cadence serve as channels for ARM products. B) Mentor, Synopsys, and Cadence want to see, and be seen by, ARM’s enormous worldwide customer base. C) ARM has the winning hand in today’s semiconductor supply chain, so either the Big Three in EDA pony up to help sponsor ARM TechCon, or the UK-based IP behemoth won’t cooperate in the EDA world; they won’t offer pointers or tool-development advice for the third-party design software that EDA vendors sell and ARM customers [might] buy.
Wednesday, August 12th, 2015
Autumn used to start in September, but now classes and conferences commence in August and vacation ends just that much sooner. Here’s a list of various events you should consider attending between now and the end of the year, with thanks to conference organizers for the associated descriptions.
Scanning the range of topics, it’s clear the combined IP and EDA industries have an increasingly broad range of interests: IoT, autos, wearables, software security, verifying/integrating IP, power, device physics, memory, embedded processors and software, sensors, MEMS, a range of standards, networking, both the professional and technical kinds, and “synergistic collaborative design” both up in the cloud and down below on solid ground.