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Posts Tagged ‘ARM’

ESD Alliance: Sonics’ Grant Pierce elected Board Chair

Thursday, February 9th, 2017

 


This week, the ESD Alliance
announced that Sonics CEO Grant Pierce has been elected chair of the organization’s Board of Directors. His election is unique in several ways: Pierce is the first CEO of an IP company to lead the Alliance; he replaces two co-chairs, Cadence CEO Lip-Bu Tan and PDF Solutions, John Kibarian; and he is only the second CEO of a non-publicly traded company to serve as Board Chair, the other being Jasper CEO Kathryn Kranen who took the reins in 2012.

When Pierce and I spoke by phone on Tuesday about his election, he noted the unique circumstances of his new leadership role: “When I joined the board several years ago, it was with the intention to add a new point of view to what was then the EDA Consortium, to help the organization reflect the emerging reality of what was happening in the marketplace with respect to IP companies.

“In some ways, the IP companies consider themselves to be a necessary evil. Every chip developed today involves some sort of third-party IP, so having a place on the Board of the ESD Alliance is essential.”

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Apocalypse soon: RISC-V channels mammals after the Asteroid

Thursday, January 19th, 2017

 


At the ESD Alliance panel on the Cadence campus Wednesday night
, it was Vista Ventures’ Jim Hogan who suggested the little open-source processor architecture called RISC-V will prove itself to be a plucky survivor when looming market realities hit 800-pound proprietary vendors like ARM and Intel. Hogan suggested RISC-V is positioned to survive that pending apocalypse just like “the mammals after the asteroid.”

Pretty dramatic stuff.

Hence it should not have been surprising, at the end of the 75-minute discussion on stage between Jim Hogan and Microsemi’s Ted Speers and SiFive’s Yunsup Lee, that I raised my hand and asked why Simon Segars was not in the room. After all, Simon Segars is both CEO of ARM and a key member of the Board of the Alliance that organized the Hogan-Speers-Lee program – a program where the emerging RISC-V movement was described as poised to upend the primacy of ARM etc.

Hogan responded to my question without answering: “Look, ARM is challenging by serving the low-cost processor market. License fees, royalty fees – that is what ARM wants for their low-power edge-based device. I think it was Simon, for example, who started talking to The Street about his economic strategy. It’s not really about what the best technology is, but about the economics. This is what gets the traction, and ARM will respond in an economic way.”

“Yes,” Ted Speers added, “and Intel and Imagination will also respond.”

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RISC-V: ESD Alliance to showcase Situational Irony on Jan 18th

Thursday, January 5th, 2017

 


One of your New Year’s Resolutions
should be to further understand the philosophy, technology, and implications of the RISC-V movement. And there will be no better way to follow through on that resolution than to attend the upcoming ESD Alliance discussion on the topic.

In a nod to the best in situational irony, the Alliance is hosting an evening event in Silicon Valley on January 18th specifically to discuss this open source processor architecture, which per some has the potential to turn ARM’s market dominance on its ear.

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DAC 2017: Deadlines for IP Submissions start November 15th

Thursday, November 10th, 2016

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

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EDA Death Spiral: Qualcomm/NXP last nail in coffin

Thursday, October 27th, 2016

 


Raise your hand if you think innovation comes out of small, nimble, edgy startups
. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.

Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.

Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.

However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.

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DVCon Munich: IP Integration, Automotive, Smart Cities, System Design

Thursday, October 13th, 2016

 


Next week, DVCon is once again in Europe, October 19-20 in Munich
. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.

It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.

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The Tate Effect: Confidence in Flex Logix Team & Technology

Thursday, September 22nd, 2016

 


Geoff Tate, founding CEO at Rambus, is busy – again.
 These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.

When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.

“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”

“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”

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IoT: The Second Coming

Thursday, August 25th, 2016

 


This week’s blog post is authored by Bill Finch, Senior VP at CAST, Inc.
, long-time provider of IP cores and platform IP products. The discussion below maps the evolution of technologies and strategies that produced today’s IoT to the critical road map needed to achieve tomorrow’s.


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IoT: The Second Coming

The second wave of the IoT is about to start. In the first wave, there was little clarity about what functionality really mattered. Engineers were tasked with getting products out ASAP. Because of the uncertainty and rush, most first-wave products were built around off-the-shelf parts made by IDMs (Integrated Device Manufacturers). The emphasis was on getting things working, not on optimization.

This will not be true in the second wave.

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Remembering Mark Templeton: One of the Greats of IP

Saturday, July 23rd, 2016

 


The semiconductor IP industry is reeling at news of the tragic death of Mark Templeton
while white water kayaking last weekend in Oregon. Well known, widely admired, and held in great esteem for both his intelligence and unassuming style, Templeton will be sorely missed, not just in the IP industry, but across the entire tech sector.

Per the Press Release: “Mark R. Templeton, 57, was a highly respected venture capitalist in Silicon Valley who used his background as an engineer to foster scientific advancement. In his capacity as a director and board member of numerous tech companies and organizations, he was instrumental in driving growth in the intellectual property market through a combination of technical and business innovation.”

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Kapow Wham Boom: Holy Acquisition, Sir Robin!

Monday, July 18th, 2016


Yep, it’s happened
. More astonishing than Brexit. Faster than a skyrocketing market cap. Stronger than any ties to Merry Old England, Apple, or ESDA. Able to leap over continents in a single bound.

Holy All-Cash-Deal, Sir Robin, ARM’s been bought by SoftBank!

For a mere 24.3 billion pounds.

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