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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

IP Sampler: Self-evident truths

October 17th, 2013 by Peggy Aycinena

A brief sampler of recent announcements on the IP front reveal distinct themes in the marketplace. IP development and integration require a viable ecosystem of suppliers and tool vendors; automotive, audio and mobile apps continue to be important targets for IP developers whose customers seek better safety, longer battery life, and truer sound (particularly for sporting events and concerts of aging rockers); IP interfaces remain crucial; and platform-based design totally depends on further enhancements in IP technologies.

Additionally, acquisitions definitely pan out for the companies smart enough to snap up the good ones: Synopsys/ARC, Cadence/Tensilica, and Imagination/MIPS.


SIP provider CAST released a reusable subsystem and suite of hardware reference designs that the company says make it easier to build video streaming into mobile and other products.

Per the company, “The new H264OIP-HDE Subsystem integrates three IP cores available from CAST: the H.264 High Profile Video Encoder core for high-quality video compression, and the RTP and UDP/IP hardware stacks for encapsulating video for Internet Protocol transmission. Flexible video, memory, and network interfaces simplify system integration, and optional logic blocks enable standalone, processor-free subsystem operation.

“Available hardware reference design systems provide a turnkey jump start to streaming system development. Reference designs for the streaming subsystem are available now for the Altera Stratix IV and Arria V families, and the Xilinx Kintex-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.”

Nikos Zervas, CAST COO, is quoted in the Press Release: “This new video over IP subsystem makes the superior H.264 compression we offer drop-in ready for high-performance, low-latency, low-energy, video streaming over Ethernet or Wi-Fi. Completing the solution are FPGA reference designs for turnkey HDMI- or DVI-to-Ethernet streaming in hardware, and customization services through which we can deliver a pre-packaged and fully verified combination of any video-in or network controllers a customer requires.”


* Cadence announced a suite of “ultra-fast” low-power analog IP products targeted at next-generation high-speed wired and wireless communications applications.

Per the company, “The Cadence data converter family includes: 7-bit 3GSPS dual ADC and DAC; 11-bit 1.5GSPS dual ADC; and 12-bit 2GSPS dual DAC. These cores can be easily combined to form a complete analog front end IP solution [and] uniquely meet the needs of designers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60 GHz spectrum with potential data throughput up to 7Gbps, as well as LTE and LTE Advanced.

“The ADC IP cores are developed with a parallel Successive Approximation Array (SAR) architecture, producing extremely fast and scalable sample rates. High Effective-Number-of-Bits (ENOB) values are achieved with a unique implementation and built-in background auto calibration, producing more accurate conversion and consistent performance. The DAC IP cores use a current switching architecture and include a digital multiplexer and FIFO for easy integration into an SoC. The DACs include digital gain control and all required reference circuitry.”

Martin Lund, SVP, Cadence IP Group, is quoted in the Press Release: “The ability to easily integrate the Cadence Data Converter IP in advanced process nodes eliminates the need to go ‘off-chip’ and allows designers to take full advantage of the system benefits of integrating both the digital and analog content into a single complex SoC. This translates to longer battery life, smaller thermal profile, and lower overall system cost.”

* Cadence also announced its Tensilica HiFi Audio/Voice DSP is the first IP core to offer a certified decoder for Dolby DS1 for Dolby Digital Plus audio streams.

Per the companies: “Dolby DS1 for Digital Plus is optimized to provide mobile users with home theater-inspired sound quality by enabling a distortion-free audio/voice boost and also by compensating for unintelligible dialogue, extreme volume variation, and deficiencies inherent in the small speakers and low-power amplifiers on most mobile devices.

“As part of the broader Tensilica DPU (dataplane processing unit) product offering, Cadence’s Tensilica HiFi Audio/Voice DSP is the most widely used licensable audio/voice DSP family, with support for over 100 proven audio/voice software packages. More than 55 companies have licensed the HiFi DSP family, and they have shipped over 200 million HiFi DSP cores in smartphones, tablets, computers, digital televisions, home entertainment systems and other devices.”

John Couling, SVP for E-Media at Dolby, is quoted: “Device makers worldwide are looking for ways to differentiate and meet consumer demands for mobile entertainment. The Tensilica HiFi Audio/Voice DSP is a proven platform that enables the most premium audio experiences today with Dolby technologies.”

* Cadence also announced it’s the first IP core supplier to offer DTS Neural Surround Support. Per the companies, “Partnered with the Cadence Tensilica HiFi Audio/Voice DSPs, DTS Neural Surround brings a home theater-like experience to automobiles and A/V receivers, significantly enhancing the sound quality of up-mixing from compressed media types like MP3.”

Jack Guedj, Cadence’s Corporate VP, IP Group, is quoted in the Press Release: “We’ve seen a growing demand from our customers and OEMs to support DTS decoders and audio solutions, including the latest DTS Neural Surround for an enhanced surround sound experience in home and automotive entertainment. Many recent sports and music broadcasts, including Rolling Stones concerts and the 2013 Super Bowl, were broadcast in DTS Neural Surround to ensure that fans received the highest level quality audio.”

Geir Skaaden, SVP of Products and Platforms at DTS, is also quoted: “Cadence continues to expand its leadership position with the Tensilica HiFi Audio/Voice DSP by bringing new, highly optimized and innovative audio solutions like DTS Neural Surround for next generation car audio processors and investing in extensive testing to ensure product robustness and quality.”


ARM and Cadence announced the companies have signed an agreement for the sale and transfer of Cadence PANTA display controller cores to ARM.

Per the companies, “The agreement enhances the companies’ long-standing ecosystem collaboration and strengthens their technical alignment. Cadence’s PANTA family of high-resolution display processor and scaling coprocessor IP cores was co-developed in conjunction with ARM and is targeted at advanced multimedia applications for high-end mobile devices with ultra-low power consumption.”

Pete Hutton, EVP and GM in ARM’s Media Processing Division, is quoted: “Display technology is critical to the mobile consumer’s user experience. The addition of the PANTA family of display cores to the ARM product portfolio will help our ecosystem of partners get to market quickly with high-end displays that are fully integrated with ARM’s leading Mali graphics and video solutions and protected with ARM TrustZone security.”

Martin Lund is also quoted: “ARM and Cadence work together closely on many levels, including IP integration, VIP for all ARM AMBA protocols, and high-performance design solutions optimized for ARM cores. As a result, both companies offer more tightly integrated solutions to our mutual customers.”


Imagination Technologies announced the first MIPS Series5 ‘Warrior P-class’ CPU, which the company says represents “a major step forward in feature set for high-performance MIPS CPU IP cores. The new MIPS P5600 core delivers industry-leading 32-bit performance together with class-leading low power characteristics in a silicon footprint up to 30-percent smaller than comparable CPU cores, making it ideal for a wide range of mobile, consumer and embedded applications.

“Building on this first important milestone in the new MIPS Series5 era, the MIPS ‘Warrior’ family of CPUs will expand over the next 12 months to comprise a compelling portfolio of 64-bit and 32-bit variants, each delivering best-in-class performance, and benefiting from the unrivaled MIPS architecture that enables seamless migration from 32-bit to 64-bit solutions.

“The P5600 supports multicore configurations of up to six cores per cluster with high-performance cache coherency, hardware virtualization, 128-bit SIMD, plus significant micro-architecture optimizations for maximizing SoC system performance. The P5600 is ideal for SoCs targeting next-generation mobile phones and tablets, connected consumer products such as set-top boxes, DTVs and multi-room multi-channel audio systems, home and office networking and micro-servers.”

Tom Halfhill, a senior analyst with The Linley Group and a senior editor of Microprocessor Report, is quoted: “As the first new MIPS core introduced since the acquisition of MIPS Technologies, the MIPS P5600 shows that Imagination Technologies is pushing the historic MIPS architecture forward.”

Tony King-Smith, EVP marketing, Imagination, is also quoted: “This is about much more than the arrival of yet another CPU IP core. This is the start of something much bigger – the rollout of a comprehensive family of next-generation CPUs that will change the CPU IP landscape forever. As we continue to roll out MIPS Series5 products to address the applications spectrum from entry-level to the high-end, we will provide levels of performance, efficiency and functionality that surpass other offerings in the market. Many more Warriors are coming!”


IPextreme announced the new ColdFire V1 Platform based on technology used in Freescale Semiconductor’s ColdFire+ family of products.

Per the companies, “The new platform rounds out an already rich offering of ColdFire cores and subsystems to provide customers with a solid roadmap of ColdFire-compatible offerings well suited for deeply embedded applications. The ColdFire V1 Platform consists of an enhanced V1 CPU core and a pre-integrated subsystem consisting of commonly used peripherals that can be configured in or out of the platform. The configuration is handled automatically from within Xena, IPextreme’s web-based IP delivery system.”

CPU Configuration Options include: single-wire debug interface, enhanced multiply-accumulate function for DSP operations, cryptographic acceleration engine, and hardware divide unit. Subsystem Configuration Options include: RAM controller, ROM controller, and CPIO controller, among others.

Warren Savage, President & CEO of IPextreme is quoted: “The semiconductor industry is moving rapidly toward platform-based design as the norm, allowing not only hardware reuse, but also to allow software reuse across multiple product lines. We have hundreds of ColdFire V1 licenses in the field, and our customers are increasingly asking us to provide them with a simple, easy-to-use platform to get their embedded products to market faster than ever.”

Geoff Lees, SVP and GM of the micro-controllers business at Freescale, is also quoted: “Availability of IPextreme’s new platform based on Freescale’s ColdFire technology is good news for ColdFire customers and the larger embedded community. IPextreme offers a solid roadmap of products that enables new applications leveraging the strength of the ColdFire architecture and ecosystem.”


Mentor Graphics announced full interoperability between the Tessent IJTAG chip-level IP integration product and ASSET InterTech’s ScanWorks platform for embedded instruments, which includes chip, circuit board and system-level IJTAG tools.

Per the Press Release, “Tessent IJTAG combined with ScanWorks lets engineers access the operational and diagnostic features of all IP blocks in the design from a top-level interface, greatly simplifying the job of integrating the hundreds of IP blocks in a typical system. Interoperability between the two solutions revolves around the IEEE P1687 standard’s Instrument Connection Language (ICL) and Procedural Description Language (PDL).

The Tessent IJTAG tool reads ICL and PDL code delivered with third-party IP blocks and verifies that it is IEEE P1687 (IJTAG)-compliant. It then generates a logic network and associated ICL to integrate all the IP blocks in a design and processes the PDL for each IP to create composite chip-level PDL. The ScanWorks product then reads chip-level ICL and PDL for use in chip debug and also re-targets the PDL to a board or system level interface.”

Kent Zetterberg, ASSET’s IJTAG product manager, is quoted: “In order for the IJTAG standard to be effective, SoC and PCB designers, as well as system-level manufacturing engineers, need an ecosystem of support from semiconductor IP providers, EDA tool providers and hardware/software debug, validation and test tool providers like ASSET. We’re working with Mentor to provide a seamless flow based on IJTAG from the IC design environment to the SoC and PCB debug, validation and test phase.”


Synopsys announced the new DesignWare ARC EM SEP (Safety Enhancement Package) Processor core designed for automotive safety-compliant applications.

Per the company, “The 32-bit ARC EM SEP processor is based on the highly efficient ARC EM4 core. It delivers performance up to 300 MHz and power consumption as low as 16 µW/MHz on typical 65-nm low power silicon processes, with integrated hardware safety features that enable ASIL D compliance in support of the ISO 26262 standard.”

“In addition, the DesignWare ARC MetaWare Compiler helps software developers accelerate the development of ISO 26262-compliant code and is undergoing ASIL D readiness certification by SGS-TUV Saar, a leading independent safety certification company.

“The combination of a safety-enhanced processor and compiler makes the ARC EM SEP core ideally suited for SoCs designed for embedded automotive applications such as movement and acceleration sensors, advanced driver assistance systems and electric power steering.”

* Synopsys also announced a range of DesignWare Interface IP on TSMC’s 20-nm SoC process. Per the companies, “Synopsys DesignWare USB, DDR, PCI Express and MIPI PHY IP on TSMC’s 20SoC process reduces risk for designers who need to implement the latest interface IP standards in their SoCs and want to take advantage of 25-percent lower power consumption or a 30-percent performance improvement offered by TSMC’s 20SoC process compared to TSMC’s 28-nm process.”

Suk Lee, TSMC Senior Director in the Design Infrastructure Marketing Division, is quoted: “The availability of Synopsys’ high-quality IP portfolio for our 20SoC customers provides a low-risk path to implementing proven IP while reducing SoC power consumption.”

John Koeter, Synopsys VP of Marketing for IP and systems, is also quoted: “By offering a broad portfolio of IP for the 20-nm process, Synopsys enables designers to more easily meet their goals of creating differentiated products with less risk and faster time to volume production, while also reducing the risks associated with moving to the 16-nm FinFET process.”


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