Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Update: IP on the move
June 20th, 2013 by Peggy Aycinena
Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.
The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”
Brian McMath, Technical Director at OCZ, is quoted in the Press Release: “We were very focused on reducing schedule risk, which made it imperative that we partner with an established vendor like Synopsys that had the proven portfolio of IP, design flows and services that we needed. The combination of Synopsys’ proven DesignWare IP, experienced design consultants and tapeout-proven Lynx Design System made it possible for us to achieve our performance goals while saving an estimated two months of schedule time.”
Per the Press Release: “CUDA 5.5 release candidate brings the power of GPU-accelerated computing to ARM platforms, the world’s fastest-growing processor ecosystem – approximately 10 times larger than the x86 CPU-based market. The new CUDA release provides programmers with a robust, easy-to-use platform to develop advanced science, engineering, mobile and high performance computing applications on ARM and x86 CPU-based systems.”
Jim Whittaker, EVP of the Processor Group at Imagination, is quoted: “With MIPS, Cavium has created some of the industry’s highest performance and most advanced 64-bit multi-core processors for networking, wireless and storage. We’re now working even more closely with Cavium to take MIPS, the industry’s most successful and widely deployed 64-bit architecture, to even higher levels of performance and innovation. Imagination’s ownership of MIPS has significantly increased the level of investment in, and support for, MIPS CPU IP core development across the entire range of 32-bit and 64-bit solutions, with a focus on hardware, software, tools and ecosystem. We are delighted that Cavium has reaffirmed its commitment to MIPS as a result.”
M. Raghib Hussain, Corporate VP/GM and CTO at Cavium, is quoted: “The MIPSr5 architecture enhancements from Imagination combined with Cavium’s in-house design expertise will help create the most advanced MIPS 64-bit processor in the industry and will serve to further extend our leadership in the network infrastructure market.”
Ashraf Takla, President & CEO of Mixel, is quoted: “GDA Technologies brings a comprehensive expertise in high-speed digital IP interfaces and the entrepreneurial spirit of a Silicon valley company that is backed by the vast resources of L&T, a fourteen billion dollar multinational conglomerate. We are delighted that GDA Technologies is joining Mixel’s MIPI Central and that we are taking our five-year-old collaboration to the next level.”
Keshab Panda, Chairman of GDA Technologies & Chief Executive at L&T Technology Services, is also quoted: “We have achieved multiple first-silicon successes with Mixel’s MIPI PHY, while supporting our mutual customers, as both a digital IP and ASIC design service provider. We are looking forward to taking this collaboration to the next level with the second-generation MIPI high-speed interfaces, a market segment that is showing rapid growth.”
According to the Press Release: “The Evatronix team will report to Martin Lund, Cadence SVP of R&D in the SoC Realization Group. Terms of the transaction were not disclosed.”
Per the Press Release: “The BA21 Low-Power Embedded Processor delivers 32-bit processing capability in a small, energy-efficient package, achieving 2.5 CoreMarks, operating up to 125 MHz, and needing under 10K gates (with a 65nm process). Its two-stage pipelined design is optimized for low power consumption in deeply embedded applications such as wireless communications or mixed-signal control. It offers a powerful step up from 8-bit microcontrollers used for such applications, as well as being a more efficient choice over larger general-purpose system processors.
Matjaž Breskvar, CEO at Beyond, is quoted: “The world’s rush towards big data accessed anywhere requires devices that can capture, process, and analyze information within severe power budgets, and this can only be achieved through highly efficient hardware designs. To address such needs, this new BA21 core applies unmatched design efficiency to the most area- and power-sensitive end of the processor spectrum, doing more work in less silicon and using less energy than any comparable 8-, 16-, or 32-bit processor. It’s the perfect fit for the next generation of intelligent sensors, deeply embedded devices, or as a helper in complex SoCs.”
C.Y. Lin, VP for R&D at eMemory, is quoted: “We have stringent verification requirements for our NeoEE product, a true rewritable memory technology implemented in CMOS with up to 100K program/erase cycles. We selected the AFS Platform because it delivers nanometer SPICE accuracy significantly faster than traditional SPICE simulators to verify and characterize our 28nm CMOS embedded non-volatile memory IP for PMICs, MCUs, RFICs, and other SoCs.”
Ravi Subramanian, President & CEO of BDA, is quoted: “Developing cost-effective and size-competitive embedded non-volatile memory is a tremendous design challenge. eMemory’s selection validates the tremendous value Berkeley Design Automation brings to semiconductor memory developers. We are delighted that eMemory has selected the AFS Platform for verification and characterization of their embedded non-volatile memory products.”
Per the Press Release: “The SSIC IP provides low-power, high-speed chip to chip interconnect which leverages existing investments in USB software and system investments. High performance and reduced power are achieved by using the MIPI M-PHY as the physical layer interface. Leveraging the MIPI M-PHY power management, the SSIC interface lowers the active power and idle power. The SSIC adapter layer IP is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.”
Andrew Haines, VP at Arasan, is quoted: “We are known for our strong position in the SD/eMMC and MIPI IP markets, but most customers are not aware of our commitment to offering superior support. Support at Arasan is provided by development engineers working on the product, guaranteeing the customer will be communicating with someone who has the highest level of knowledge. This level of support is standard, regardless of where the support request is coming from.”
Tags: Andes Technology, Arasan, ARM, BDA, Beyond Semiconductor, Cadence Design Systems, CAST, Cavium, eMemory Technology, Evatronix, GDA Technologies, Imagination Technologies, MIPS, Mixel, NVIDIA, OCZ Technology Group, Synopsys