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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

DAC 2013: IP news in advance of Austin

 
May 30th, 2013 by Peggy Aycinena

** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits.


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Cadence Design Systems announced it has completed the acquisition of Cosmic Circuits, a provider of analog and mixed-signal IP cores. Per the Press Release: Cosmic Circuits offers silicon-proven IP solutions in connectivity and advanced mixed-signal technologies in the 40nm and 28nm process nodes, with 20nm and FinFET development well underway.

The Cosmic Circuits team will report to Martin Lund, Cadence’s senior vice president of research and development, SoC Realization Group. The completion of this transaction further expands Cadence’s IP portfolio, strengthening its solutions to address mobile, cloud/datacenter and Internet-of-things market opportunities.


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CAST announced that its H.264 video encoder IP cores now feature an option for ultra-low latency video encoding, enabling near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST’s hardware stacks for fast, processor-less video processing. The sub-frame rate control feature for ultra-low latency is now a standard part of the intra-only version video encoder cores and available from CAST worldwide. These new ultra-low latency intra-only encoders are sourced from CAST technology partner Alma Technologies.

Per the Press Release: The H.264 video encoder cores available from CAST have always allowed a designer to regulate latency down to a few frames through a sophisticated rate control algorithm. The intra-only versions of these encoders can now go further, giving designers the ability to regulate latency at a deep sub-frame level. This enables latencies under 20ms for 30 frames per second video, and under 10ms for 60fps.


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Forte Design Systems and CircuitSutra, an ESL IP and services provider, announced they will partner to provide design services throughout India to support the growing SoC market.  As part of the agreement, Forte and CircuitSutra will co-develop ARM AMBA AXI and OCP-IP models compatible with Forte’s Cynthesizer System HLS, and will deliver onsite consulting and training for Cynthesizer users in India.

Brett Cline, VP of Marketing and Sales at Forte, is quoted in the Press Release: “CircuitSutra’s mission to help semiconductor companies and electronics systems companies adopt SystemC-based ESL methodologies neatly corresponds to Forte’s mission. India offers tremendous opportunity to expand SystemC HLS usage and we believe CircuitSutra will play a big role in this effort.”

Umesh Sisodia, CEO at CircuitSutra, is also quoted: “Forte’s continued focus on SystemC-based HLS is impressive, as is its commitment to support and service. The ESL IP that we will co-develop will help mutual customers to quick start their HLS-based design projects.”


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Kilopass Technology and UMC announced a new technology development agreement, which calls for Kilopass to port its non-volatile memory IP to two of UMC’s leading edge 28nm processes: the High-K Metal Gate 28HPM targeted at portable device SoC manufacturers and the poly-gate 28HLP targeted at consumer electronics SoCs. The initial Kilopass-UMC partnership started in 2010 with UMC’s 40LP process, which is available now.

S.C. Chien, VP of Customer Engineering & IP Development & Design Support at UMC, is quoted in the Press Release: “To ensure our customers have access to not only UMC’s eFlash, eE2PROM, eMTP, eOTP and eFuse, but also the best third-party non-volatile memory IP at the 28nm node, we are happy to continue our partnership with Kilopass to ensure that their variety of anti-fuse NVM IP offerings is available on our 28nm process family.”

Charlie Cheng, President & CEO of Kilopass, is also quoted:  “Enablement of our NVM IP offerings on UMC’s major 28nm node provides an expanded IP portfolio in advanced process nodes that UMC can offer its customers.  And it broadens Kilopass’ reach into mobile device SoCs and consumer electronics SoCs where UMC’s 28nm processes have a growing presence and expanding market share.”


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Sonics recently announced that ARM has licensed Sonics’ patent portfolio, currently consisting of 138 properties, for use in ARM products and specifications. The companies say this agreement “signals the closer cooperation between Sonics and ARM on Sonics’ next generation advanced power management and on-chip interconnect technologies for leading edge SoCs.

“Close interaction between system processors, on-chip networks, and the attached IP subsystems and cores are important to minimizing overall system power. The ability to keep cores switched off for much longer periods of time, along with the ability to turn devices on and off much more rapidly, will enable significant power savings over current solutions.”

Grant Pierce, Sonics CEO, is quoted in the Press Release: “This agreement with ARM demonstrates our ongoing commitment to make SoC design easier for our customers. Working in partnership with ARM, Sonics will continue to deliver innovative solutions that address some of today’s most difficult challenges when building advanced SoCs. We welcome our enhanced relationship with ARM and look forward to providing products in support of the company’s large ecosystem.”


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Synopsys announced the DesignWare ARC EM Starter Kit for the ARC EM family of embedded processor cores. The Starter kit enables “out-of-the box” software development, debugging and system analysis and includes four pre-installed FPGA images for the ARC EM4 and EM6 processors, 32-bit DesignWare cores optimized for use in embedded and deeply embedded applications.

The ARC EM Starter Kit includes a base board and daughter card. The daughter card features a Xilinx Spartan-6 LX45 FPGA, an on-board 125 MHz clock generator, 128 MB of DDR3 memory and 16 MB of flash memory. The flash memory supports the storage of application software and contains four pre-installed ARC EM processor core bit files that can be selected with a DIP switch. The base board allows multiple connectivity and configurable I/O options, making it easy to add circuitry and build subsystems around the EM processors. Quick system configuration enables software development prior to final SoC hardware availability.

Michael Mo, senior director of product marketing at Amlogic, offered testimonial in the Press Release: “The combination of high performance, low power and small footprint of the DesignWare ARC EM4 processor made it ideally suited for our connectivity products Synopsys’ ARC EM Starter Kit offers a low-cost hardware platform that enables designers to quickly explore attributes of the EM cores and get an early start on the development of features that will differentiate their ARC-based designs.”


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