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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

IP @ DAC: a session a day keeps the doctor away

April 4th, 2013 by Peggy Aycinena

Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars.

Here’s your DAC planning guide …

Sunday Workshop: Driving Quality to the Desktop of the DAC Engineer

Time: 1:00 pm to 6:00 pm

Summary: This workshop will demonstrate a complete flow, using de facto industry standards, for designing, packaging, and integrating semiconductor IP, insuring that quality metrics are observed and preserved throughout the flow to the DAC engineer’s desktop. The workshop will showcase, in a realistic fashion, how engineers from different companies use their proprietary tools and technology to work together.

There will be ample time provided for open discussion throughout the workshop—audience members are encouraged to ask questions and share their thoughts and impressions at each stage of the flow. The workshop will conclude with a roundtable session with the presenters.

TSMC will discuss the TSMC 9000 quality standards. Atrenta will demonstrate the use of SpyGlass and its IP Kit for the analysis of IP against a set of standard quality metrics. Sonics will demonstrate the creation of configurable IP and validating it with Atrenta tools. IPextreme will demonstrate the use of Xena for storing and managing completed IP products, and the use of Atrenta’s tools.

Organizer: McKenzie Mortensen / IPextreme

* Warren Savage / IPextreme
* Michael Cizi / IPextreme
* Dan Kochpatcharin / TSMC
* Mike Gianfagna / Atrenta
* Frank Ferro / Sonics

Monday Tutorial: Packaging IP and Assembling SoCs Using IP-XACT-IEEE1685 Standard

Time: 11:00 am to 1:00 pm, 2:00 pm to 4:00 pm, 5:00 to 7:00 pm

Summary: This all-day tutorial will appeal to those new to the IP-XACT- IEEE1685 standard and offer additional insight into more advanced IP-XACT topics. The presenters are IP-XACT experts and will begin with an introduction to the fundamental concepts of IP-XACT, followed by a series of ‘how-to’ topics. Attendees will initially be brought through IP Packaging topics such as creation of bus definitions, bus interfaces and HW/SW interface representation. Integration topics will focus on representing hierarchical designs through instantiating components and connectivity.

The 2nd half of this tutorial will focus on more advanced topics including generators, SCR compliancy checks, channels, bridges, parameters and design configurations. The presentation technique will focus more on visually presenting the IP-XACT concepts rather than walking through XML snippets.

Organizers: David Murray / Duolog Technologies,  Kathy Werner / Southwest Reuse

* David Murray / Duolog Technologies
* John Eaton / Ouabache Designworks
* Vasant Kumar Easwaran / Texas Instruments
* Nagendra Gulur / Texas Instruments
* Kamlesh Kumar Pathak / STMicro
* Sylvain Duvilliard / Magillem Design Services

Tuesday Special Session: My IP is Better than Yours, but Does Anyone Care?

Time: 10:30 am to 12:00 noon

Summary: Product differentiation is all the rage. With so many IP components becoming standard, it seems that configurability of IP is the only effective method to allow product designs to differentiate in any significant way. User-driven and provider-offered configurability has become a key advantage in product design. Yet too much configurability makes for enormous design and verification challenges. In this special session, key technical experts from IP providers and integrators will discuss the pros and cons of configurability and answer the question of “how much is enough”. Learn how to use your IP most effectively!

* Chris Rowen / Tensilica [“Goldilocks & the Three Bears of Programmability“]
* Jose Nunez / Freescale [“Challenges of Integrating External IP“]
* Laurent Moll / Arteris [“SoC Product Differentiation Using Configurable Interconnect IP“]

Wednesday Pavilion Panel: IP Pitfalls, Avoiding the Wild Ride

Time: 10:30 am to 11:15 am

Summary: We’ve all heard horror stories about IP, about high integration costs and slipped schedules. So, how do you determine the true impact of IP on project time-to-market and budget, buying versus building your own? Learn how experts quantify the “buy” decision and tradeoffs in IP business models, and in cost and quality at and various levels, blocks to subsystems.

Moderator: Warren Savage / IPextreme

* John Swanson / Synopsys
* Keith Odom / National Instruments
* Hans Bouwmeester / Open-Silicon


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