Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
ARM & SNPS: implementing big.LITTLE
March 21st, 2013 by Peggy Aycinena
If you thought about going to the Synopsys Users Group meeting next week in Silicon Valley, there’s at least one topic that would make it worth your time: This week ARM and Synopsys announced “optimized 28-nm Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters, as well as the CoreLink CCI-400 cache-coherent interconnect.”
The reference implementations are currently available, and include “scripts, floorplan, constraints and documentation” – scripts that are built on Synopsys’ tool Reference Methodologies and are optimized for high-performance cores. Clearly attending SNUG would clarify what you need to know to use all of this, but first apparently you need to understand ARM’s big.LITTLE processing. Which is what?
Per the company: “ARM big.LITTLE processing is an energy saving technology where the highest performance ARM CPUs are combined with the most efficient ARM CPUs in a combined processor subsystem to deliver greater performance at lower power than today’s best-in-class systems. With big.LITTLE processing, software workloads are dynamically and instantly transitioned to the appropriate CPU based on performance needs.”
Did you follow that? Okay, because the stuff ARM and Synospys announced this week is targeted at SoC designers who can “use these Reference Implementations to create high-performance Cortex-A15 and energy-efficient Cortex-A7 processor clusters, and can combine them with the CCI-400 interconnect to create a big.LITTLE processing system that delivers increased product functionality with longer battery life.”
So here’s the circular logic. You need the big.LITTLE processing concept to drive your use of the ARM_Synospys Reference Implementations, which will allow you to create Coretx-based processor clusters, which can be combined with CCI-400 interconnect technology to create big.LITTLE processing systems.
To understand it all, you’ll need to:
Especially big.LITTLE things.