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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Reflex CES: Linking IP, FPGAs, and IEDM

December 13th, 2012 by Peggy Aycinena

France-based Reflex CES [Custom Embedded Systems] announced this week what the company calls “the industry’s first release of the Reflex CES Aurora-like IP core based on Altera FPGAs. The core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs.”

Sylvain Neveu, Reflex CES Co-founder and CEO, is quoted: “With our Reflex CES Aurora-like IP core, designers can easily migrate to new FPGA families with minimum risks, reuse their previous designs, and choose the best FPGA technology for their boards and systems using the Aurora protocol.”

So if that’s an Aurora-like IP core, what’s an Aurora IP core? The answer is, it’s from Xilinx:

Aurora is a scalable, lightweight, low-latency, link-layer protocol that is used to move data across point-to-point serial links. It provides a transparent interface to the physical serial links, allowing upper layers of proprietary or industry-standard protocols to easily use these high-speed serial links. Aurora uses the least possible amount of logic while offering a rich, highly configurable feature set, increasing bandwidth through bonded lanes. It is an open protocol and free of charge.”

But if Aurora is open protocol and free of charge, why is Reflex CES doing something that’s Aurora-like? Maybe it’s because what they’re providing “creates interoperability” between Xilinx and Altera, a Xilinx competitor.

Returning to the December 12th press release from Reflex CES: “Based on the Aurora 8B/10B, an open standard protocol used to transport data with higher connectivity performance for chip-to-chip and board-to-board architecture, the Reflex CES Aurora-like IP Core allows designers to move data from point-to-point across one to sixteen serial lanes at 3.125 Gbps.”

This is all pretty interesting stuff, particularly if you were in Session 25 on Tuesday morning this week at IEDM in San Francisco where Altera offered up a no-nonsense tutorial on FGPAs, how they work, how they’re designed, and how they stack up against ASICs. It was hard to understand why the room was totally full for the Altera presentation: Don’t the device experts who come to IEDM understand FPGAs? Aren’t they the ones who facilitated the development of the technology? Do they really need to attend FPGA 101?

Apparently they do, and who cares as long as the learning continues. And, as long as FPGA-based IP continues to become available in greater and greater quantities to those who need it.

The fact is, FPGAs are rocking the tech world whether in end-use reconfigurable systems, in pre-production ASIC emulation and validation systems, or in universities where students studying design can actually have access to low-cost, real-world implementations of their projects. They’re graduating in droves with far more familiarity with FPGAs than with ASICs.

Given all this, you’d be well advised to stay in close contact with companies like Reflex CES who understand that from IP vendors to system designers to students everywhere, FGPAs are crucial to the future of computing.


More from the press release …

“The Reflex CES Aurora-like IP Core offers the freedom to choose the best FPGA technology and accelerate time to market for embedded military and telecommunications/networking applications. It offers a fully compliant implementation of the Xilinx Aurora 8B/10B scalable, link-layer protocol for high-speed serial communication, and allows for communication between FPGAs through a backplane.

“The core offers user flow control, native flow control, immediate and completion mode, and modules to convert interfaces to and from streaming Advanced eXtensible Interfaces (AXI). This low protocol overhead IP core offers customers minimal data rate transfer latency with minimal logic resources – less than 900 equivalent logic cells for a 1 lane configuration- for cost effective implementation.”


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