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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Esencia: from services to software

 
December 6th, 2012 by Peggy Aycinena

Last month, Lou Covey posted comments regarding a blog posted here about Esencia Technologies, the company that received Software Best-in-Show at ARM TechCon. He took issue with my suggestion that it was unclear why Esencia received the award.

Covey’s comments prompted my phone call with Karl Kaiser, VP of Engineering at Esencia, who explained: “EScala is a design platform that takes a C algorithm for things like MP3 encoders, and creates an IP block for the design – a reprogrammable core for the target architecture. EScala allows you to generate a core that fits your algorithm.

“At Esencia, we have provided a lot of ASIC design services and wanted to find a way to simplify the traditional RTL flow – architecting, partitioning, implementing, and writing the testbench. EScala is a result of that effort and is unlike anything else on the market.

“Up until now, if you needed a core you had to shop around for different models that all required you to make trade-offs. Now when you license EScala you can build your own core, customizing it around things like number of registers and ALUs, or choosing area over speed or performance. The tool makes you sweep through the various options and lays out the tradeoffs associated with the various choices. More importantly, you don’t have to be a core expert to use the tool, which is very cool.”

Having been singled out at TechCon, I asked Kaiser what’s next for the company.

He said, “Although we just launched EScala earlier this year – based, by the way, on internally developed technology – we are not a new company. What we’re building today has been in the work for 6 years. Historically, Esencia was an ASIC IP and design service company, but our work developing EScala has widened our efforts.

“Now we see ourselves as a hybrid between an EDA and an IP company and have begun targeting FPGAs and the embedded market, which is why we decided to exhibit at ARM TechCon where we announced EScala’s floating point feature.

“As a self-funded startup, we were quite pleased to get the conference award, although we didn’t know in advance we were in the running. For us, the award confirms that our future is full of opportunity. There are big questions in the industry around design development time and designer productivity – particularly, right now at 20 nanometers. We fully expect to be part of the solution to those questions.”

That’s all well and good, I said, but surely there’s competition.

Kaiser replied, “Some would see tools from Synopsys or Target as competitors, but we don’t see it that way. Those tools are for CPU architects that want to build custom cores and need full control over the instruction set and CPU architecture like pipelining. EScala operates at a higher level of abstraction; users do not have to be CPU experts.”

Does that mean ARM is a competitor, I asked.

Kaiser chuckled, “That wouldn’t make sense for us as all. We see EScala more as a companion technology sitting next to an ARM CPU. In fact, we are an ARM Community member and enjoy the support of ARM. Our award at TechCon confirms that support!”

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White Paper …

Esencia has published a White Paper discussing the foundational technology at the core of EScala. You can read that publication here on the company website.

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