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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

ARM TechCon Best-in-Show Software: Esencia Technologies

November 22nd, 2012 by Peggy Aycinena

IP provider Esencia Technologies received a Best-in-Show Award in the Software Category at the recent ARM TechCon 2012 in Silicon Valley. It’s not clear what the criteria were for the award, but it was Esencia’s EScala Design Platform that garnered the accolade, according to the company’s website. Based in San Jose and founded in 2006, the company says they focus on delivering “pre-verified IP cores” to their customers.

This is interesting, because sitting in the audience in early November when UBM’s Brian Fuller made the award, it was noted that Esencia was chosen as Best-in-Show due to the innovative nature of its IP-generating software, not because of the quality of the pre-verified IP it delivers. After all, how could Fuller or his organization know how good the IP cores are that Esencia produces?

So what does it mean to automatically generate an IP core? Does it mean that you input some sort of declaration of specification, and then a black box IP generator pops out your desired block after the appropriate buttons have been pushed and bells and whistles have sounded?

Certainly such a black box is the apparent intent of the French-startup ZettICE, which is developing “flexible generators of FPGA and ASIC IP for complex applications ranging from linear algebra to multimedia domains.” It’s true, ZettICE is in the very early stages of incubation as a company and there is, as yet, no product to vet for either Best-in-Show awards or market traction.

However, if Esencia is doing the same thing now that ZettICE says it hopes to do someday, then a) Esencia should be putting in a bid for Best-in-Show at SAME Forum as ZettICE did this year, and b) the following details from the Esencia website detailing the EScala Design Platform describe that innovative black box IP generator that Brian Fuller hinted at from the stage at the Santa Clara Convention Center.

  • Define algorithms in C/C++ language
  • Generates architecturally advantaged high performance core and scheduled code
  • Fast and automated flow enables greater understanding of implementation options and trade-offs
  • Fast models, design data base, compilers, and tools generated on the fly

Now, if we could just get some kind of similarly automated black box type of tool to seamlessly integrate that IP core into the larger system, then we’d really have something to tout as Best-in-Show and it wouldn’t just be at SAME or ARM TechCon. It would be Best-in-Show on a Global Scale, and having invented a better mouse trap the world would beat a path to our door.


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One Response to “ARM TechCon Best-in-Show Software: Esencia Technologies”

  1. Lou Covey says:

    The award for Esencia had to do with the expansion into floating-point architecture in the Escala platform, not for the platform itself. That represented a technological innovation making the addition of floating point, rather than fixed point, affordable and easier to do in a core. Since Esencia is producing revenue without venture funding after two years, one might assume that what they make actually does work and is a foundational reason that ARM accepted them as a partner and gave them the award.

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