Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Elsip: Data Management Engine IP
October 4th, 2012 by Peggy Aycinena
Swedish startup Elsip launched its first product on October 2nd, the Data Management Engine [DME], which the company says “is a programmable and configurable synthesizable IP block that solves cache coherency, memory consistency, virtual address translation and dynamic memory allocation for distributed, private or shared memories in heterogeneous and homogeneous architectures.”
I spoke with Elsip CEO Adam Edstrom at the Sophia Antipolis Microelectronics Forum in France on October 3rd. He told me Elsip is based on research out of the Royal Institute of Technology in Stockholm, in particular the work of professors Axel Jantsch, Ahmed Hemani, and Zhonghai Lu. The company was incorporated last year, but the patent-pending product has been many years in the making.
Per Edstrom: “The world is going to multicore, but many areas like robotics, embedded systems, and military systems are not using multicore because the demands of shared memory cannot be met. With DME, however, we are providing a scalable solution to the problems that occur when there are lots of cores on a chip, and lots of memory. The user assigns one DME per core and because the DME is programmable with application specific micro-code, when there are multiple kernels trying to access the same memory, problems do not arise.”
Edstrom noted that the principle competitors today for Elsip’s new product are solutions being developed and supported internally at semiconductor companies. I asked him why those companies don’t continue to solve the problem on their own.
He said, “It’s not a core business for them. In addition, they are solving things in an ad-hoc way, using [techniques] that do not scale to the next project and therefore cannot be reused. Also, getting the wrong data during program execution is not easy to track. It is not found in simulation, and only maybe in debug. Yet when [such errors occur], the results can be disastrous.
“As a results, there is a lot of interest in our product from semiconductor companies in Europe, the U.S. and Asia. To our knowledge, these companies have not seen anything like our solution that actually solves their problem.
“The feedback we have received on DME so far has been very promising. As the number of cores increase, our technology will be needed by many companies as we help debunk the myth that people cannot cope with multicore.”
Additional details …
“In a minimal instantiation, the DME consumes about 34K NAND gates, running at 1.4 GHz at 20 mW in a 40nm standard CMOS technology.”
Tags: Adam Edstrom, Ahmed Hemani, Axel Jantsch, cache coherency, Data Management Engine IP, DME IP, dynamic memory allocation, Elsip, memory consistency, multicore, Royal Institute of Technology in Stockholm, SAME Forum, virtual address translation, Zhonghai Lu