Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Celebrating Accellera’s UVM: Now it’s IEEE 1800.2
April 27th, 2017 by Peggy Aycinena
The effort has consumed upwards of 10 years, and represents thousands of man-hours of effort, consultation, compromise, consensus building, rinse and repeat. Over and over until the final product was polished, presented and approved by the IEEE. Not an easy process by anybody’s estimation.
When we spoke by phone this week about the Accellera announcement, I asked Tom Alsop [Principal Engineer at Intel] how difficult the whole thing had actually been.
He chuckled slightly: “For us, it was fairly difficult.”
“It was our first time for going through the whole process and there was a significant learning ramp starting with a brand new IEEE specification. Without the help we got from IEEE, and Stan Krolikoski at Accellera [and Cadence], we couldn’t have done it.
“There were all kinds of issues in understanding how to take the Accellera specifications and [translate them] into the correct format for IEEE.”
“For instance,” Alsop continued, “we could not use the term donate – as in, this portion of the standard was donated by an individual or a company. We had to use the term contribute. Luckily, we had Stan helping us throughout the process, understanding the logistics of setting up the document and getting it contributed to the IEEE.
“Also, Jonathan Goldberg [IEEE Standards Association] held our hand throughout the process, helping to get everything organized and setting up Joe Daniels [legendary EDA documentation veteran] to do all of the documentation.
“Overall, it just took a lot of time and years of effort on the part of many people.”
Is the IEEE process so complex and specific that it discourages people from submitting potential standards?
Alsop replied promptly, “We were never discouraged. But it did take a lot of time.”
Does IEEE provide a recipe for all of this?
Again he replied promptly, “Yes, very much so, with detailed explanation of the procedures.
“As chair [of the group], I needed to read all of that documentation and insure we were very thorough in following the process.
“Above and beyond that, if I didn’t understand something, I would meet with Jonathan and ask questions and call on my experience with SystemVerilog.”
“All great stuff,” I said. “Can you give me the elevator pitch of what Accellera is announcing?”
“IEEE 1800.2 is a universal verification specification,” Alsop said, “for how to do validation, particularly with respect to the reuse of verification collateral in terms of a base class library. It enables reusable components that can now be shared, and raises those specifications to the level of an IEEE standard.”
“And,” Alsop added with emphasis, “it has been 10 years in the making!
“The completion of this work is very significant because it allows all of the EDA industry – all of the vendors out there who provide verification collateral – to share that across all the different vendors, and across all the high-tech companies that use verification collateral.
“How important is that? Very important. It’s not just critical for a few high-tech companies in Silicon Valley – we have major automotive companies, other companies like Boeing, customers and users across many industries who will benefit enormously from this new standard.”
Did all of these companies actually contribute ideas for the IEEE 1800.2?
“Yes,” Alsop replied, “and I was really surprised.
“I know that help with developing standards can ebb and flow in terms of contributions. But when we kicked off this IEEE effort, we had never had more contributors. In fact, we had 14 different companies participating. It was really surprising how much interest there was.”
What motivates companies to be involved in this kind of work? Why not rely on their own proprietary standards?
“Yes,” Tom said, “there are rouge companies who will go off and do their own standards, and we all know examples like this. But the three major EDA vendors support this verification methodology.
“So, if you are an end-user – a high-end company trying to bring IP in for your chip design – the large EDA companies are providing the test verification collateral in UVM. It is the de-facto standard, so there really is no choice but to [align] with it.”
“It sounds like this has been an all-consuming effort for you for a long time,” I noted. “Now that the standard’s done, will you have a lot more free time?”
Again Alsop chuckled, “Well, I do plan to get back into the IEEE thing in a couple of years, but I have handed off the implementation effort for 1800.2 to Justin Refice [Nvidia] to revise. He will drive those efforts within Accellera.
“Then in a year or two, when they’ve got an implementation released, I’ll step back in. Meanwhile, I have so many other things I’m focusing on at Intel.”
Why is Alsop opting not to be involved in the implementation?
“Generally, even within Intel,” he responded, “I try to find opportunities for people to grow.
“I’m 21 years in the industry at this point, and although I enjoy it – sometimes it’s good to pass on responsibilities to others and let them grow.
“I’ve been doing it for so long, it’s time to pass the reigns onto someone else. I tend to look for someone who is very responsible, and responsive, and Justin was very much the obvious choice to continue with the work.”
Alsop offered ringing endorsements for everyone who’s been involved over the last 10 years.
“We simply could not have done all of this without a committed team, particularly the great support from the Accellera UVM Working Group. In fact, we have had very significant help from many people – a lot of help from the Board of Directors of Accellera and numerous people at IEEE.”
“We cannot not emphasize enough,” he concluded, “that this has been a team effort from the very beginning.”
Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of EDA and IP standards, announced today that IEEE 1800.2 Standard for Universal Verification Methodology (UVM) has been approved by the IEEE Standards Association (IEEE-SA). The standard will be available for download later this spring at no charge under the Accellera-sponsored IEEE Get Program.
Since its inception in 2010, the IEEE Get Program has resulted in more than 83,000 downloads, providing pre-paid access of electronic design and verification standards to engineers and chip designers worldwide. IEEE 1800.2 will be released under the IEEE Get Program as soon as it is published.
UVM has achieved industry-wide success as the standard used by verification engineers to verify complex designs. As an important companion to SystemVerilog, it improves interoperability and reduces the cost of IP development and reuse for each new electronics project. UVM has a very active worldwide user community and forum, and its LinkedIn group has almost 7000 members.
About IEEE 1800.2
The IEEE 1800.2 Standard for UVM establishes a set of Application Programming Interfaces (APIs) that are used to define a base class library (BCL) definition which engineers employ to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard. The goal of the IEEE 1800.2 standard is to improve productivity for electronics systems development by making it easier to verify design components with a standardized verification representation that can be used with various automation tools, helping to lower development costs and improve design quality.
“The UVM Working Group has done an outstanding job developing UVM 1.2,” commented Lu Dai, Accellera Chair. “Now that it is an approved IEEE standard, the Accellera UVM Working Group will continue to provide improvements to the base class library implementation and updates to the UVM User’s Guide. The UVM Language Reference Manual will become responsibility of IEEE, where many key members of the Accellera UVM Working Group also participate.”
“As a world class standards development organization, our mission is to provide a high quality, market relevant standardization environment,” stated Konstantinos Karachalios, managing director of IEEE-SA. “Our partnership with Accellera helps us to provide even more standards to the design automation industry reaching design engineers around the globe.”
Tags: Accellera, Accellera Systems Initiative, Cadence, IEEE 1800 SystemVerilog standard, IEEE 1800.2, IEEE Get Program, IEEE Standards Association, Intel, Joe Daniels, Jonathan Goldberg, Justin Refice, Konstantinos Karachalios, Lu Dai, NVIDIA, Stan Krolikoski, SystemVerilog, Tom Alsop, Universal Verification Methodology, UVM, UVM Working Group