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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

RISC-V: ESD Alliance to showcase Situational Irony on Jan 18th

 
January 5th, 2017 by Peggy Aycinena


One of your New Year’s Resolutions
should be to further understand the philosophy, technology, and implications of the RISC-V movement. And there will be no better way to follow through on that resolution than to attend the upcoming ESD Alliance discussion on the topic.

In a nod to the best in situational irony, the Alliance is hosting an evening event in Silicon Valley on January 18th specifically to discuss this open source processor architecture, which per some has the potential to turn ARM’s market dominance on its ear.

Of course, the irony comes in the realization that the CEO of previously autonomous ARM (now a subsidiary of SoftBank) is still a renowned member of the Board of Directors of the ESD Alliance. Yes, situational irony at its best.

But that’s not the only reason you should plan to attend the ESDA discussion, set to unfold in Building 10 on the Cadence campus starting at 6:00 pm on Wednesday, January 18th.

Also a draw will be discussion moderator and entrepreneur/thought leader Jim Hogan and his guests – Rick O’Connor, Executive Director of the RISC-V Foundation, and Yunsup Lee, CTO at SiFive.

Meanwhile, before you start laying down plans to navigate the horrendous Silicon Valley traffic on January 18th in order to get to Cadence in time for the Alliance’s now-legendary pre-panel wine and cheese – it would be best if you’re somewhat up to speed on what RISC-V is, and hopes to become.

To do that, here are six things you need to know.

1 – RISC-V comes out of U.C. Berkeley and is partially funded by DARPA.

2 – It’s a (dangerously) open source processor architecture developed by a team of researchers including Cal’s Krste Asanovic and Dave Patterson.

3 – Per Wikipedia: The RISC-V authors aim to provide several CPU designs freely available under a BSD [Berkeley Software Distribution] License, which allows RISC-V chip designs to be either open and free, like RISC-V itself, or closed and proprietary. This is unlike the alternative OpenRISC cores, which under a GNU General Purpose License requires derivative works to be open.

4 – Also per Wikipedia: The RISC-V authors have substantial research and user-experience validating their designs in silicon and simulation.

5 – RISC-V is all the rage among Academics and other Tech Intelligentsia, with no less than six events showcasing the topic last year – at locations as diverse as the campuses of Oracle in January and Google in November, at ESC Boston in April, at the Design Automation Conference in June, at a very well-attended conference at MIT in July dedicated solely to the topic, and at the Silicon Valley IoT Meetup in October.

6 – Companies currently involved in implementations using the RISC-V CPU architecture include SiFive, Bluespec, Google, HP Enterprise, Lattice, Mellanox, Microsemi, Oracle, Rambus, Nvidia, Codasip, UltraSOC, Adepteva, and ASTC. Universities include IIT Madras, University of Cambridge, University of Bologna, and ETH Zurich, among others.

However, the fact that the ESD Alliance is choosing to showcase the RISC-V movement at their upcoming meeting is more important than all six of these factoids combined – the situational irony involved, notwithstanding.

Because, per the ESD Alliance: “The speakers on January 18th will describe the path from inception to the open source RISC-V ecosystem, explore whether an open source architecture is appropriate for IoT processing needs and what that means for startups and innovation.”

This discussion will be informative and useful.

Hurry and register here because seating is limited.

And so is the wine and cheese.

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