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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

DAC 2017: Deadlines for IP Submissions start November 15th

 
November 10th, 2016 by Peggy Aycinena


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

First of all, yes. Some really smart people in IP have fought really hard for a number of years to get this kind of program ‘real estate’ dedicated to the subject of developing, verifying and integrating reusable IP blocks. Respect the uphill struggle they’ve had to endure by taking advantage of this opening they’ve afforded you.

Second of all, despite the rise of vendor-specific shows – not the least being, SNUG, CDNLive, Mentor’s User Group, and ARM TechCon – all of these companies, and more, continue to invest time and resources in the Design Automation Conference. They do this because, although they might find it easier and cheaper to walk away, they still know the industry values this venue. If that were not the case, you would not find Synopsys, Cadence, Mentor, and ARM on the IP Track review committee.

Third, and finally – it should be of intense and relevant interest that next year’s DAC is being chaired by a true industry icon: Michael ‘Mac’ McNamara. Mac not only has decades of distinguished EDA service to his credit, he is currently the CEO of a company called AdaptIP.

In other words, at the very top of the leadership of the DAC Executive Committee sits an individual who fully comprehends the importance and pivotal nature of reusable design blocks, and the impact these design structures have had, and will continue to have, on the emergence of phenomenal semiconductor design and devices. McNamara understands IP, and now so does the entire ecosystem that supports the Design Automation Conference.

You should recognize this reality and embrace the opportunity: To further your own research, your own commercial enterprise, and the future of IP-driven design.

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