Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Menta eFPGA IP: Antidote for evolving Standards and ECOs
June 16th, 2016 by Peggy Aycinena
This month is clearly a busy one for Menta, and for more reasons than just exhibiting in conference venues 7000 miles apart. On June 6th, the company announced its “next generation of embedded programmable logic IP cores for SoCs.”
I spoke by phone with Menta’s biz development guru Yoan Dupret about the announcement, in the week prior to DAC, and asked if eFPGA IP is difficult to manufacture within a chip.
He said, “It’s hard IP, made for big logic targets, and not too difficult to manufacture because it only includes standard cells, which is one of the strengths of our technology. As a result, our customers are able to verify everything we do inside their standard flows.”
Quoting from the Menta press release during our conversation, “Embedding an FPGA fabric as an IP core in an SoC allows semiconductor designers to update the silicon at will, post production, thereby eliminating the cost and time associated with re-spinning silicon,” I asked Dupret why all logic on an SoC should not be executed using eFPGA technology.
He responded, “Compared to other cores, a reconfigurable core can take up 8-to-10 times [more real estate], so it should only be used when it’s really needed [because it may prevent] a chip from meeting its design targets.”
“Nonetheless,” he added, “we are getting more and more traction with the designers, because there is so much need for programmable fabric.”
Dupret referenced his presentation: “There are five different problems, as you can see on Slide 3, which our eFPGA solves. One is that the specifications are not well-defined when a design project starts.
“Second is that several customers and/or markets require multiple variants of an ASIC. Third, the same ASIC needs to evolve over time in a specific portion of the logic – inkjet printer cartridge chips, as an example.
“Fourth, sensitive circuitry often requires tuning and debugging – something that needs to happen post-production. And fifth is when a CPU co-processor is required, which would otherwise entail additional cost and power-loss from an extra FPGA component in the design.”
“In all of these are scenarios,” Dupret emphasized, “our IP is a game changer, particularly for any engineering team aiming to meet compressed time-to-market windows with the confidence that their systems can accommodate evolving standards or additional customer-designed features.”
In other words, in the costly world of semiconductors, it continues to be a balancing act between meeting product requirements and providing post-production flexibility because those requirements changed even as the product came off the line. Menta’s eFPGA IP is providing an antidote for the anguish that’s associated with those types of engineering change orders.
The origin of the company’s name is, apparently, an interesting story in itself. Laurent Rougé, Menta founder, was a Franck Herbert Dune fan when he was a teenager.
When creating Menta, he was reminded of a specific type of humanoid in the books – the Mentat – who are very clever and mimic the abilities of computers. As Menta was created, long after Laurent read Dune for the last time, the ending ‘t’ of Mentat slipped away and Mentat became Menta.
June 6, 2016 – Menta announced deliver of the industry’s highest performing embedded programmable logic IP for SoCs. The programmable logic, available as both custom and pre-defined IP cores, is based on Menta’s proven eFPGA fabric, optimized to deliver the industry’s best combination of performance, reduced sized, and low power consumption.
Version 4 of Menta’s custom and pre-defined eFPGA IP cores will benefit from a boost in performance, area usage, and lower power consumption.
Menta’s Yoan Dupret is quoted in the Press Release: “Over three product generations, Menta’s eFPGAs have stood apart from the competition in terms of flexibility and ease of use. The boost in performance and support of additional process nodes with our next generation of eFPGAs will bring the benefits of post-production RTL modification to a wider range of applications.”
The company is also announcing expanded support for additional technology nodes: In addition to TSMC’s 28-nanometer HPM and STMicro’s 28-nanometer FDSOI, Menta’s IP is now optimized for GlobalFoundries 14-nanometer LPP process.
In addition, Menta can deliver custom IP cores with embedded logic blocks, embedded custom blocks, and embedded memory blocks – each of which are customizable in type, number and size to address various markets and applications.
Menta provides both Origami Designer to define custom IP-based on the designer’s RTL, and Origami Programmer, an EDA tool that supports design from HDL design to bitstream, with synthesis, mapping, and place-and-route.