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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

IP @ DAC: Sound & Fury or Smoke & Mirrors

 
April 14th, 2016 by Peggy Aycinena


IP now dominates design automation
, evidenced in no small measure by ARM’s seat at the head of the table for the ESD Alliance, ESDA being an important sponsor of the Design Automation Conference. Everyone seems to agree that IP reuse is the only way complex mega-systems of the 21st century can be designed, so not surprisingly the DAC program now reflects that reality. There are sessions every day categorized as being IP-related, but are those designations accurate?

I would argue that a lot of the content that’s sitting in the IP Track at DAC is really just about design, and not specifically about IP-based design. To prove that point, below is a complete listing of the sessions in the IP Track that’s set to air between June 6th and 9th at DAC in Austin. Those that are legitimately about IP are bolded, sessions that actually talk about using IP. Those not bolded are ‘just’ about design, or are merely high-level nattering about superficial issues associated with IP reuse.

Conclusion: the number of IP-related sessions are far fewer than one would hope. If IP is this important, why aren’t there more sessions that are really about IP? Is there a conspiracy here?

Fortunately, this next week I’m talking at length with Warren Savage. As CEO of IPextreme, his knowledge about the technology and business of IP is pretty encyclopedic. I will run my conspiracy theory past him: DAC wants you to believe they believe in IP, but in fact the conference is still more about design automation, not about using silicon IP to enhance the process. EDA vendors still rule the roost at DAC.

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* IP TRENDS AND REQUIREMENTS [Monday, 10:30 am to Noon]
Sessions include presentations that demonstrate leading-edge trends and requirements covering the IoE, emerging as the next frontier of connectivity to conquer, as well as functional safety as an emerging requirement for SoC Designers and vendors of silicon IP.
Chair: ARM’s Simon Rance
Speakers: Synopsys’ Jamil Kawa, Cadence’s Nick Heaton, ARM’s Andrew Hopkins and Lauri Ora
Sponsor: ChipEstimate.com

* TUTORIAL: TAMING THE DARK HORSE, VOLTAGE-MARGIN MINIMIZATION FOR MODERN “REAL-WORLD” ENERGY-EFFICIENT COMPUTING [Monday, 10:30 am to Noon]
Tutorial provides an overview of low-power circuit and architecture techniques with a system-level context.
Speakers: Univ of Washington’s Visvesh Sathe, ARM’s Shidhartha Das

* MIPI ALLIANCE AND IP: A PERSPECTIVE FOR THE MOBILE AND MOBILE-INFLUENCED MARKETS [Monday, 1:30 pm to 3 pm]
Tutorial will provide: 1) An overview of MIPI Alliance, 2) MIPI Specification Framework and Roadmap, 3) A technical tutorial on two of MIPI Alliance’s most widely adopted specifications (Camera and Display), and two of MIPI Alliance’s newest specifications (Audio and Sensor).
Chair: Lattice Semi’s Claude Moughanni
Speakers: MIPI’s Peter Lefkin, Synopsys’ Hezi Saar, Cadence’s Sachine Dhingra
Sponsor: ChipEstimate.com

* LANZA’S TECH VISION CHALLENGE: DARING TO MOVE TO OPEN SOURCE [Monday, 2 pm to 2:45 pm]
The emerging IoT market is destined to upend that time-tested “advanced-node” model as developers opt for older, less costly process technologies using commodity design tools and selecting proven IP blocks to efficiently assemble chips. Might open-source EDA tools and IP become a viable or winning combination that enables low-cost design of an IoT SoC?
Moderator: Lanza TechVentures’ Lucio Lanza
Speakers: eSilicon’s Mike Gianfagna, IPextreme’s Warren Savage, Scientific Ventures’ Mark Templeton, eFabless’ Mikale Wishart
Organizer: Adapt-IP’s Mac McNamara

* LOW POWER IP [Monday, 3:30 pm to 4 pm]
Explore the “Impact of Leakage & biasing on Power in 22FDX Process” and how “Analog Driven Power Estimation for Mixed Signal IPs” matter to IP designers.
Chair: Mentor’s Farzad Zarrinfar
Speakers: INVECAS’ Krishnan Subramanian, Nagaprasad Ponna, Tirumala Srikanth Singari, Apache’s Sankar Ramachandran; Intel’s Shovan Maity, Rupak Ghayal, Santosh Nene, Babu Ramki S.
Sponsor: ChipEstimate.com

* MINIMIZING SOC POWER CONSUMPTION: A TOP-DOWN DESIGN METHODOLOGY OR BOTTOMS-UP STARTING WITH PROCESS SELECTION PROBLEM? [Monday, 4 pm to 5 pm]
Panel will discuss implementation techniques and trade-offs for designing ultra low-power SOCs, ASSPs, and ASICs.
Moderator: Semiconductor Engineering’s Ann Mutschler
Speakers: Microsoft’s Aditya Mukherjee, Mentor’s Saurabh Kumar Shrimal, Soitec’s Carlos Mazure, NXP’s Ronald Martino, TSMC’s Lluis Paris
Organizer: Mentor’s Farzad Zarrinfar
Sponsor: ChipEstimate.com

* IP ECOSYSTEM MANAGEMENT [Tuesday, 10:30 am to 11 am]
Session explores modern IP management conundrums of “I Didn’t Mean to Steal Your IP …” and encrypting IP cores With gate-level simulation capabilities.
Chair: Intel’s Heather Monigan
Speakers: PWC’s Eric Stein, IPextreme’s Warren Savage: Univ Wisconsin’s Parameswaran Ramanathan and Kewal Saluja
Sponsor: ChipEstimate.com

* SOLVING THE DESIGN COST PUZZLE: HOW IP FITS [Tuesday, 10:30 am to 11 am]
ESDA and Semico will address trends and issues driving the rapidly growing market for third-party IP.
Speaker: Semico’s Jim Feldhan
Organizer: ESDA’s Bob Smith

* FISH FOOD FOR THOUGHT: CONSOLIDATION TREND IN THE IP ECOSYSTEM GOOD FOR THE INDUSTRY? [Tuesday, 11 am to Noon]
The Commercial IP Ecosystem is growing and projected to sustain growth, yet the pool seems smaller, year over year. Is current trend a hindrance or catalyst for innovation? What challenges would IP companies expect when swimming in these waters? What conditions may re-populate the pool? Who ultimately prospers: investors or end customers?
Moderator: IEEE’s John Blyler
Panelists: Sankalp Semi’s Samir Patel, Leyden Technologies’ Dennis Segers, Design Rivers’ Camille Kokozaki, Lattice Semi’s Laxman Vemury
Organizer: Intel’s Heather Monigan
Sponsor: ChipEstimate.com

* RISC-V: INSTRUCTION SETS WANT TO BE FREE [Tuesday, 1 pm to 1:30 pm]
A free ISA is a necessary precursor to future hardware innovation. There’s no technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
Speaker: UCB’s Krste Asanovic

* DESIGNING WITH RISC-V [Tuesday, 1:30 pm to 3 pm]
This session consists of a brief RISC-V overview followed by four tutorial presentations.
Chair: Cadence’s Andrea Kroll
Speakers: RISC-V Foundation’s Rick O’Connor, SiFive’s Andrew Waterman, Draper’s Andre DeHon, IowRISC’s Alex Bradbury
Sponsor: ChipEstimate.com

* EVOLVING IP INTERCONNECTS & VERIFICATION [Tuesday, 3:30 pm to 5 pm]
This session will explore the evolution and progression of interconnect IP and the challenges facing IP synthesis and verification.
Chair: Cadence’s Andrea Kroll
Speakers: Open-Silicon’s Dhananjay Wagh and Bhupesh Dasila; Synopsys’ Nivin George, Venkataraghavan Krishnan; Methods2Business’ Dejan Dumic, Farhad Mighani, Marleen Boonen, Nemanja Kondic, Daniel Kesler, Miroslav Drobac, Adapt-IP’s Farhad Mighani, ARM’s Mike Eftimakis; Lattice Semi’s Chris Kung, Chirag Dhruv, Sanket Shah; Nvidia’s Elliot Koch
Sponsor: ChipEstimate.com

* SYSTEM IP CONFIGURATION AND VERIFICATION [Wednesday, 10:30 am to 11 am]
Session addresses how intelligent IP configuration and verification of infinitely configurable cache-coherent interconnect IP can improve system design for IP engineers.
Speakers: ARM’s Simon Rance, David Murray; Arteris’ Rohit Bansal
Sponsor: ChipEstimate.com

* OPEN SOURCE: SOFTWARE, MODULES, SYSTEMS, AND NOW IP AND CHIPS? [Wednesday, 11 am to Noon]
Open source processor core IP is causing a stir. Is this a change the industry needs?
Moderator: SemiWiki’s Don Dingee
Panelists: Texas Tech’s John Leidel, IBM’s Randy Swanberg, TIRIAS’ Paul Teich, Rackspace’ Aaron Sullivan
Organizer: Cadence’s Priyank Shukla
Sponsor: ChipEstimate.com

* WHY IP SUBSYSTEMS AND WHY NOW? [Wednesday, 1:30 pm to 3 pm]
The session will consider various aspects of the emerging the IP Subsystem market.
Chair: IPextreme’s Warren Savage
Speakers: SRC’s Richard Wawrzyniak (Organizer), Sonics’ Drew Wingard, Synapse Design’s Marco Brambilla
Sponsor: ChipEstimate

* HOW DO WE MAKE IP REUSE WORK? [Wednesday, 3:30 pm to 4:30 pm]
Various factors have made IP reuse an arduous journey. Representatives from the design, provider and semiconductor communities will discuss what ails the IP industry and what can be done to improve IP reuse for analog and digital design.
Moderator: ARM’s Brian Fuller
Panelists: eSilicon’s Mike Gianfagna, Samsung’s Rwik Sengupta, ClioSoft’s Ranit Adhikary, Synopsys’ John Koeter

* HIGH-LEVEL SYNTHESIS: REACHING FOR THE STARS! [Thursday, 1:30 pm to 3 pm]
Session papers focus on enhancing HLS technology, describing techniques for selecting promising micro-architecture directives, building IP libraries for data structures to enable broader deployment, and using HLS to improving circuit reliability.
Chair & Co-Chair: Mentor’s Andres Takach and Kyoto Univ’s Takashi Sato
Speakers: Univ of Mass’ Cunxi Yu, Maciej Ciesielski, IBM’s Mihir Choudhury, Andrew Sullivan; National Univ of Singapore’s Guanwen Zhong, Alok Prakash, Tulika Mitra, Peking Univ’s Yun Liang, Univ of Valenciennes’ Smail Niar; Cornell’s Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang; Imperial College London’s Shane Fleming, David Thomas

* DESIGN/IP TRACK POSTER SESSION [Monday and Tuesday, 5 pm to 6 pm]
Per organizers: “The limited time available in the Design/IP Track session program was exceeded by the quantity of great submitted content, posters based on these papers will be presented in the Design/IP Track.”

By my estimation, however, only 6 of the 58 posters offered over the 2-day poster session can be considered relevant to IP. Those posters include …

* Layout density verification for seamless hard-IP Integration [Intel’s Samichi S. and Madan
Lal]

* Managing Complex Hierarchical Design Data [GlobalFoundries Greg Ford and Bertram Bradley]

* Die Sizing Bound By Peripheral Bumps And IPs [Open-Silicon’s Kavana V.]

* Power and Test Time reduction through Codec Sharing and Core Wrapping [Synopsys’ Rahul Anand, Salvatore Talluto, STMicro’s Shiv K. Vats, Marco Casarsa, Harish Kumar]

* Methodology for Leakage Power Optimization Of GHz A53 ARM Cores [Qualcomm’s Raghav Gupta, Apurva Chaure, Sanjeev Srivastava, Dorado’s Mihir Kumar]

* Voltage Drop Aware Early Power Grid Optimization on DSP core of 14-nm smartphone chip [Qualcomm’s Rajesh Mallina, Aravind Ramanujam, Manoj Gunwani, ANSYS’ Vinayakam Subramanian, Mahesh V. Yatagiri]


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One Response to “IP @ DAC: Sound & Fury or Smoke & Mirrors”

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