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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

SNPS’ Custom Compiler: closing the FinFET productivity gap

April 7th, 2016 by Peggy Aycinena

Synopsys Marketing Director and long-time EDA contributor Dave Reed
 talked recently about the company’s new, highly anticipated product release, Custom Compiler.

“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”

Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”

There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.

“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.

“Also, the tool takes routine things and adds constraints. Now when the user connects one transistor – where there might be dozens of constraints because it’s a device array, now the user only has to draw the connections and all of the requisite constraints [appear].”

I asked the proverbial question: Why is the user still involved at all? Why can’t the process be automated once and for all?

Dave answered, “Yeah, unfortunately analog synthesis is still beyond what we can do. It’s only after typing in the constraints that you can automate [the design process].

“Knowing that, we still wanted to piggyback on what designers are doing today. Using this new tool, the designer can say, this is the device pattern I want, and re-do that pattern implementation automatically.

“You can call it a symbolic edit, something that looks for a common pattern already built into the library. And if it’s not there, the tool adds the pattern to the library. This means that the senior designers can continue to lay down the patterns, and the junior people can implement them.”

Sounds great, I said, but what happens when the current generation of analog designers retire?

Dave said, “Hopefully using this tool, we will have captured their input and their knowledge; the template library will have captured their expertise. If a pattern [emerges] that is missing from the library, the tool can save it forever.”

He noted that Synopsys is very excited about the potential unleashed with Custom Compiler: “For years, people have been thirsty for better productivity in custom layout.

“By combining technologies we acquired from SpringSoft [2012], Ciranova [2012] and Magma [2012], with contributions from our own internal development teams, we believe we have produced something to meet that need.

“We not only have three different press releases with testimonials from customers [STMicro, GSI Technology, Asahi Kasei Microdevices], we have also successfully deployed the tool for our own internal IP designers and have measured results to prove its effectiveness.”

Expect to see a lot of interest in Custom Compiler at DAC 2016, per Dave: “The people who are coming to Austin in June will definitely have FinFETs on their mind – and Custom Compiler!”


Press Release, 30 March 2016 …

Synopsys announced Custom Compiler, “a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours. [The tool takes] a fresh approach to custom design by developing visually assisted automation
technologies that speed up common design tasks, reduce iterations and enable reuse.

Visually Assisted Automation includes:

* Custom Compiler Assistants are productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

* Layout Assistants speed layout with visually guided automation of placement and routing. The router is ideal for connecting FinFET
arrays or large-M factor transistors.

* In-Design Assistants reduce costly design iterations by catching physical and electrical errors before sign-off verification.

* Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs.
Template Assistants actually learn from the work done with the Layout Assistant’s placer and router. They intelligently recognize
circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a
template to the new circuits.”

Antun Domic, EVP/GM of Synopsys’ Design Group, is quoted: “Legacy custom design tools have not kept pace with the exponential growth in design complexity.In particular, the growing number and complexity of FinFET design rules pose significant challenges for layout designers. Custom Compiler’s innovative assistants enable designers to address the most difficult layout challenges while significantly improving FinFET design productivity.”


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