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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Sonics: Busy Days, Dark Silicon Knights

 
June 24th, 2015 by Peggy Aycinena

These last several months have been busy for Sonics: Release of the latest edition of the company’s “flagship” NoC, SonicsGN 3.0, featuring Sonics’ interleaved multi-channel technology; Release of Version 8.0 of SonicsStudio, the company’s SoC development environment with “improvements for designer productivity and power analysis”; Announcement of Sonics’ ICE-Grain Power Architecture, “a complete power management sub-system comprised of configurable hardware IP blocks, embedded control software, and integrated design tool environment”.

Of the three announcements, the last is the most profound, offering a better, smarter technique for building power management into systems that include Sonics IP. Power is of great concern to anyone working in silicon today, and of even greater concern to those whose business model includes selling both IP and services to the industry.

Drew Wingard, distinguished co-founder & CEO of Sonics, is one of those concerned, articulating the situation in detail on Monday, June 8th, at DAC where he addressed an SRO audience of 150+ technologists anxious to learn more about low power IP. Proving himself one of Sonics’ true Dark Silicon Knights, the following is a snapshot of Wingard’s comments.

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Taking Advantage of the Dark Silicon Opportunity …

Mobile devices today, smartphones, tablets, notebooks, devices for the IoT, are constrained by limitations in battery technology. There are power problems at the other end of the form-factor spectrum as well; consider the resource demands of mega-data centers.

A ton of techniques have been have been pursued for reducing power consumption on-chip, but by every report architectural choices have the greatest impact for low-power success. Strategies include fine-grained clock gating, course-grained clock gating, source clock divide, source clock gating, dual voltage switching, static body bias, static voltage switching, retention voltage switching, power switching, etc.

Despite all of those choices, transistors in silicon today don’t turn off much anymore and dark silicon has become a problem – transistors sitting idle, but drawing power. But dark silicon can also offers opportunities, were it possible to identify the regions of an SoC that will be idle, a region in the subsystem, IP core, or sub-module. Those regions identified, it should be possible to partition the design to isolate such regions, and with that knowledge select the appropriate power-savings technique, the power state transitions would be controlled quickly and safely.

The challenge is in enabling the best power domains for the SoC, determining the standard fabric and the best natural choice for creating boundaries at the bus interfaces between the domains. Partitioning the fabric at the power-domain boundaries, however, complicates the design process.

There are more questions: What is a ‘safe’ operation of an SoC with powered-down domains? The system needs an ‘initiator agent’ to clear the path to the target to enable a safe shutdown of any particular power domain. Also: Let’s say a network can automatically ‘wake-up’ a component when it’s needed, that same initiator agent needs to know which component to wake up.

All of this points to the need for a scalable, modular power management technique. Until now, the conventional method has been via the software, notifying the CPU that it’s time for a power down, an interrupt generated. Unfortunately, that process takes a lot of power and the CPU is not very fast in responding.

This is why many in the industry are following Sonics’ lead, seeing the distinct benefits in hardware-controlled power management techniques. The results are faster power-up from standby to active, faster retention of a power state, and faster power-up from shutdown to active.

For Sonics, Dark Silicon Control requires a dual manager that handles both network issues and power – a highly integrated, power-aware, on-chip network. This can be achieved using an integrated tool chain that allows the designer to create an automated, fine-grained, highly responsive solution that’s built right into the hardware. The results, per Sonics’ research, have been astounding.

Better clock/power domain partitioning has yielded 79% fewer always-on gates for wearable processors, while design-optimized fine-grained clock gating has yielded 44% lower active power states compared with synthesis-based clock gating. Automatic/instant course-grained clock gating has produced 95% lower idle power when compared with synthesis-based clock gating, and hardware-based power state transitions operate 10-20x faster than transitions achieved through optimized software-based controls.

The results and message are clear: Dark silicon is an opportunity to think about how we do design. Let’s make low-power designs using the appropriate IP in the infrastructure. Let’s control Dark Silicon through the Hardware.

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Busy Days at Sonics …

* May 12th – Sonics introduced the ICE-Grain (Instant Control of Energy) Power Architecture is the semiconductor IP industry’s first and only complete power management sub-system comprised of configurable hardware IP blocks, embedded control software, and integrated design tool environment.

With the ICE-Grain Power Architecture, SoC designers partition their chips into much finer “grains,” which enables up to 10x faster and more precise power control. Power “grains” are very small sections of an SoC that include functional logic that can be individually power controlled using one or more savings methods.

A grain is connected to one or more clock domains and attached to at least one power domain, and includes defined signals and conditions for power control. Grains are often an order of magnitude smaller than conventionally independent power or clocking domains, and multiple grains can be composed into larger hierarchical grains.

The ICE-Grain Power Architecture automates the tasks of grain connection and management by synthesizing both central and local control circuitry blocks for the greatest total SoC power reduction.

Drew Wingard is quoted in the Press Release: “Our goal with the ICE-Grain Power Architecture is to give system architects the IP, drivers, and automation tools they need to address power reduction early in the SoC design process where it proves most effective.

“To save power, designers must power-down parts of the SoC as quickly as possible to eliminate leakage current, and then power the parts back up just in time. Our fine-grain approach controls power in hardware for much faster switching between states. This approach also implements dynamic voltage and frequency scaling to take advantage of the high dependence of active power on voltage.”

* June 8th – Sonics introduced SonicsStudio 8.0, the latest release of its next-generation SoC development environment that includes improvements for both designer productivity and power analysis. In Release 8.0, Sonics has added major new features to all three areas of SonicsStudio: the Director user interface, the underlying SonicsStudio generation tools, and the automated development flows for stimulus generation, simulation, synthesis, and performance/power analysis.

Drew Wingard is quoted in the Press Release: “Release 8.0 of SonicsStudio incorporates many new capabilities our NoC customers requested to improve productivity using the environment and produce better quality of results in silicon.”

* June 23rd – Sonics released SonicsGN 3.0, the latest version of the company’s flagship NoC. SonicsGN 3.0 expands on the interleaved multi-channel technology (IMT) that has been patented and proven in SonicsSX and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools.

SoC architects using SonicsGN 3.0 can eliminate multi-channel DRAM access bottlenecks with IMT and reduce layout tool iterations with flexible user control of hierarchical RTL partitioning and re-timing stage insertion.

Drew Wingard is quoted in the Press Release: “Use of multi-channel DRAMs and memory sub-systems is now pervasive in SoC designs, for example, in mobile applications where maximizing memory throughput takes precedence over increasing memory capacity.

“To address this trend, we’ve expanded IMT in SonicsGN 3.0 to give SoC architects much more effective management of transaction concurrency and memory sub-system performance in their designs. At the same time, we’ve enhanced SonicsGN’s handling of hierarchical partitioning and re-timing to provide better layout guidance when designers generate their RTL netlist for physical synthesis and detailed place & route.”


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