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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

IP @ DAC: Design reuse still not for faint of heart

April 16th, 2015 by Peggy Aycinena

Building on last year’s success, the 2015 Design Automation Conference in San Francisco is offering even more substantial content in the track centered on silicon IP and design reuse. Reading through the list of topics, speakers, and companies set to be featured across a diverse set of sessions from June 7-9 at Moscone Center, two things are obvious.

One, a lot of work has been done to assemble all of this. And two, it’s possible the thorny issues surrounding IP reuse may never go away: integration, verifying quality, convincing staff to use design blocks that originate outside of the group, and dealing with the massive amounts of data that IP selection and reuse generates.

* Sunday June 7th, IPextreme’s Warren Savage will chair the most important IP-centric session at DAC, a day-long workshop, Enterprise-Level IP Management for the DAC Semiconductor Professional, that consists of six modules:

1. Levels of design reuse, how much is appropriate.
2. IP business models including the most commonly used legal and licensing agreements.
3. Common reuse issues at the technical, organizational, and business level.
4. Creating a reuse-aware culture by setting up incentive programs to encourage engineers to employ IP reuse.
5. Keeping track of everything, accurately managing massive amount of data from suppliers, successful chips, and design files.
6. Incorporating user feedback loops, sharing information to improve the overall system.

* Low Power IP: Chaired by Mentor’s Farzad Zarrinfar, this Monday morning session on June 8th includes implementation techniques, selection tradeoffs, and optimization for ultra-low power IC will be presented.

The concluding panel will be moderated by PRN Engineering Services’ Dave Bursky, and will showcase Sonics’s Drew Wingard, TSMC’s Luis Paris, Calypto’s Saurabh Kumar, Microsoft’s Aditya Mukherjee, and Mentor’s Shankar Krishnamoorthy.

* IP Implementation: Chaired by ARM’s Brenda Westcott, this Monday afternoon session includes discussion of synthesis constraint methodologies for high-speed SERDES, techniques for mapping analog IP to different foundries, on-chip POP package co-design for DDR interfaces, using SystemC for hardware/software for ULP Wi-Fi IP.

The concluding panel will be moderated by Semiconductor Engineering’s Ed Sperling and will showcase Xilinx’ Darren Jones, Cavium’s Surya Hotah, and EZchip’s Bob Doud.

* Subsystem IP & IP Integration: Chaired by TSMC’s Clark Chen, this late-afternoon session on Monday includes discussion of design for analytics, IoT processor IP platforms, ISO 26262 automotive safe certification, and vision processing subsystems.

The concluding panel will be moderated by Semiconductor Engineering’s Ann Mutschler and will showcase Synopsys’ Navraj Nandra, Cadence’s Thomas Wong, Global Unichip’s Lewis Chu, and ARM’s Leah Schuth.

* Verification/Validation of IP: Chaired by Warren Savage, this Tuesday morning session on June 9th will detail verification strategies to deal with IP reuse complexities while working to meet project schedules.

The concluding panel will be moderated by Semiconductor Engineering’s Brian Bailey, and will showcase Breker’s Tom Anderson, S2C’s Toshio Nakama, Synopsys’ Bernie Delay, OneSpin’s Raik Brinkmann, and Cadence’s Frank Schirrmeister.

* IP Strategies & Management: Chaired by Intel’s Heather Monigan, this Tuesday afternoon session will address IP quality metrics, how to decide which vendor should provide which class of IP, and how to keep track of internally generated IP.

The concluding panel will be moderated by Chip Design’s John Blyler, and will showcase Cadence’s Martin Lund, Synopsys’ John Koeter, Imagination’s Krishna Yarlagadda, and TSMC’s Suk Lee.

* IP Reuse Poster Session: Companies showcased among the 93 posters showcased in this concluding late-afternoon session on Tuesday will include Nvidia, Atrenta, STMicro, ST-Ericsson, ANSYS, Intel, Aquantia, elitePLUS,  Open-Silicon, Broadcom, Apache, Tortuga Logic, AMD, Freescale, Oracle, Cadence, Marvell, Xilinx, Mentor, Samsung, IBM, SMIC, Synopsys, NSCAD, Renesas, Qualcomm, CPqD R&D, Infineon, OmniPhy, ARM, Codasip, Exar, Huawei, Cisco, STATS ChipPAC, elitePLUS, University Federal do Rio Grande do Sul, University of Central Florida, Sandia National Laboratories, Flex Logix Technologies, IP-nest, Soft Machines, Altera, Zeidman Consulting, eSOL, and Oski Technology.


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