Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
eSilicon: Kick the IP before you buy
January 15th, 2015 by Peggy Aycinena
In any marketplace, it’s the buyer’s problem to know in advance of a purchase whether the product is worth the money. In the IP marketplace, the problem’s particularly intense, because until the block is operating within the target environment, it’s close to impossible to know if it’s worth the money.
Today eSilicon is offering what appears to be a reasonable solution to the dilemma. Per the company, “now you can get immediate answers to your power, performance or area questions with pre-loaded data for eSilicon memory compilers and I/Os using the eSilicon IP Marketplace environment.”
The environment allows the prospective buyer to generate dynamic, graphical analysis of power, performance and area data, to view the chosen data graphically, to build and download a complete chip memory subsystem, generate and download IP front-end views, run simulations in the user’s own environment, and make changes over time, only paying for the IP when the project’s ready to tape out.
This all seems like pretty radical stuff in a marketplace where everybody’s struggling to know if the IP they’re going to use is the right choice.
If you want to know more about this analysis environment, eSilicon’s hosting a webinar on January 21st from 9:00 am to 9:30, California time. Surely it’s worth 30 minutes to find out if IP Marketplace is something that would be useful.
You can register here to tune in.
Per the company, “Since 2000, eSilicon has specialized in designing, productizing, and manufacturing ASICs for our customers: system OEMs and fabless semiconductor companies. Our strength is in developing and delivering complex chips. We develop an average of 20 new chips per year, which keeps our skills at the cutting edge. We have delivered first-time-right silicon across over 250 tapeouts at 28nm-250nm.”