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Graham Bell
Graham Bell
Graham is Sr. Director of Marketing at Real Intent. He has over 20 years experience in the design automation industry. Occasionally he writes blogs for the Dominion of Design. The views and opinions expressed in this blog are his alone and not those of his employer.

Hard IP, an introduction to increasing ROI for VLSI Chip designs

 
March 27th, 2012 by Graham Bell

I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at EDACafe.com.   With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on EDACafe.com.  Here below is a copy of the Preface to the book and introduces the material.  I hope you find it interesting and useful.

PREFACE

A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.

In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.

Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up!

In this book, we explore IP (Intellectual Property) reuse in terms of VLSI chips. IP reuse is one of the answers to the many concerns about necessary gains in productivity, the time – to – market and timing closure. IP reuse simply means that, instead of developing a design from scratch every time we need a new chip, we will take advantage of chips that already exist and have proven themselves. However, for these existing chips to be truly useful and provide competitive performances, they need to be rejuvenated somehow to meet higher performance requirements. So we need to show how we can reuse IP. how to improve the performance of the reused chips, and even how we can improve manufacturability of the reused IP.

Today, synthesis is the most common path to complex VLSI designs. Design teams and management, in other words the infrastructure dealing with the creation of complex VLSI designs, are set up to facilitate the process of synthesizing new chips. Consequently, it is not surprising that resynthesis is also the primary focus of IP reuse today. A high-level description of a design previously fabricated in some now outdated technology is resynthesized to a different library of a more advanced technology. This approach is generally referred to as Soft IP reuse because the IP database is in the form of some high-level language in software. Hence, Soft IP.

There is, however, another way to reuse existing designs. An increasingly accepted and more direct path to reusing existing designs is to start with the data that describes the physical layout of a chip. This physical layout data that was used to make the masks to fabricate the chip can be reused, rejuvenated and the postlayout optimized. Rejuvenation of a VLSI chip starting with Hard IP means that an existing and proven layout has to be retargeted or migrated to a more advanced technology, one that allows smaller minimum critical layout dimensions. This approach is generally referred to as Hard IP reuse because the IP database is the physical layout. We use terms such as retargeting and migration interchangeably, meaning that the physical layout of a chip is laid out anew, according to the different design and layout rules of a higher performance semiconductor process. When we discuss more involved processes such as IP optimization, IP creation or process modifications, such an increase in manufacturing yield, we often use more generic terms like Hard IP engineering.

THIS BOOK’S FOCUS

This book primarily focuses on Hard IP reuse. However, we will see that Soft and Hard IP methodologies complement each other in many situations. In fact, in those situations, both are virtually necessary. We need to keep in mind that all Soft IP will eventually become hard and may require some postlayout, which means Hard IP-based performance optimization or solving some unexpected problems, especially those related to timing.

In Chapter 7. we also examine the two approaches to compare their respective strengths in relationship to the application and sometimes the form in which the IP is available.

Synthesis-based Soft IP reuse is assumed to be well known as a methodology, and it is described here in minimum detail. There is a lot of literature on the subject of synthesis and the recently published RMM thoroughly covers Soft IP reuse [1].

On the other hand, Hard IP reuse is newer in its presently emerging form. It is not well known or understood and we think it is a critically important methodology for Very Deep Sub-Micron (VDSM) technologies (we generally refer to it as simply Deep Sub-Micron (DSM) in this book). In addition, the dramatic increase in impact of physical layout on the performance of DSM VLSI chips leads to totally new approaches for performance optimization, IP creation and manufacturing yield manipulations. These approaches are closely linked to the techniques used for Hard IP engineering.

It is hoped that this book will explain one way to take advantage of the newly gained power of semiconductor physics that is reflected in the substantial effects of physical layout and its manipulation on chip performance.

OVERVIEW OF THE CHAPTERS

In chapter 1, we examine some of the reasons why IP reuse has become such a hotly debated issue. Incredible time-to-market pressures, shorter market windows, a rapid increase in chip complexity with a corresponding increase in design time coupled with very expensive processing lines that need to be “fed,” all suggest a careful analysis of the design process. Although processing lines are currently full, fluctuations in the economy and the relentless march towards smaller layout dimensions and increasingly complex chips suggest potential vulnerability. Should we really design every new chip from scratch or in some cases take this new and promising IP reuse route? We discuss why an IP reuse methodology may make a lot of sense today and in the future.

In Chapter 2, we provide a description of how to retarget existing Hard IP. We show how libraries, memories, data paths and entire chips can be retargeted from process to process. Designs with proven track records will get a “facelift” and once again be competitive. We compare past methodologies such as linear shrinks with today’s polygon-by-polygon re-layout to the exact process layout rules. This approach is generally referred as compaction, although it is really a readjustment of layout dimensions, allowing an enlargement or reduction of any layout geometry. With the rapid advancement of VLSI design into DSM technologies, linear shrinks arc no longer adequate and do not take full advantage of very extensive and expensive progress made in processing technology. It will become clear how a sophisticated migration approach, based on polygon compaction, can provide superior results.

In Chapter 3, we examine another aspect of compaction: Performance optimization through layout manipulation for DSM technology chips. We will demonstrate that this back-end layout optimization is complementary to any front-end design methodology, yielding substantial performance improvements. In the past, the active part of a circuit was optimized, but it is now necessary to optimize the interconnects together with the active parts as inseparable pairs. Issues such as signal integrity, electromigration, interconnect-to-interconnect capacitive loading and excessive power dissipation are becoming so important that layout optimization may be a must, not just a luxury.

In Chapter 4, we examine the application of compaction – not as an afterthought once a design has already been laid out – but as a productivity enhancing step during the physical layout design. When carefully designing the layout of a building block, such as a library element, a memory cell, a macro, the layout has to comply with the design rules imposed by the process and the desired electrical behavior of the building block. Instead of observing these burdening rules during the design process, we can leave it to the incremental compaction steps during the design process or at the end of a design cycle to enforce all the rules and user inputs. We will examine the benefits of this “carefree” layout design.

In Chapter 5, we discuss some of the special challenges faced and solved with Hard IP engineering. Digital circuits has been the focus up to this point. What about the migration of analog or mixed signal designs? Another interesting challenge is hierarchy maintenance through Hard IP migration. For much of the Hard IP migration done up to now, the hierarchy in the source layout gets lost during the retargeting process. The newest migration approaches allow a complete maintenance of the hierarchy from layout to re-layout and we will discuss this capability. Design guidelines for simplifying Soft IP reuse have been given in the recently published RMM [1]. What about guidelines for minimizing difficulties for Hard IP reuse? Hard and Soft IP reuse enable an efficient S-o-C methodology by integrating various existing designs in one chip. What are the major challenges and hopefully solutions to overcome the difficulties encountered in such an S-o-C methodology? Finally, Design for Manufacturing (DfM) is currently a hot issue. The same methodologies used for sophisticated retargeting can be used to improve DfM.

In Chapter 6, we discuss some of the tools now available in the industry and tools that would be helpful for Hard IP retargeting to yield maximum benefits. And, as is the case for many “point solutions” in the EDA industry, compaction should become an integral part of a modern design or reuse flow. As minimum layout dimensions continue to shrink, this seamless integration will undoubtedly take place.

In chapter 7, we compare “design from scratch” with Soft IP and Hard IP reuse. We review today’s design flows for a VLSI design for various methodologies. This will lead to an appreciation of where the main work is performed and to an understanding of the bottlenecks that will affect the time-to-market and the cost of chips. The risks of design from scratch versus IP reuse, the costs of the tools needed to successfully accomplish all the tasks to be done as well as the skill levels required to do the jobs are critical. Return On Investment (ROI) is another angle and measure in comparing the three approaches discussed here. Why not benefit from existing and proven designs through reuse? Reuse is considered by many people to be the only long-term strategy for solving the present productivity dilemma in the chip design industry. The benefits of Soft and Hard IP reuse should become clear in these discussions.

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