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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

HLS Vision: Sanjiv Kaul’s betting his career on it

May 15th, 2014 by Peggy Aycinena

Calypto Design Systems is having quite a year. First the company announced that 2013 was its highest revenue period ever; then they announced that new offices have been opened in Korea; and most recently, Calypto named long-time EDA exec Mark Milligan as Vice President of Marketing. Previously, Milligan served as VP of Marketing at CoWare and VirtualLogix, VP of Marketing for Functional Verification at Synopsys, and VP of Corporate Marketing at SpringSoft before it was acquired by Synopsys.

Given this level of activity, it was interesting to sit down recently and talk in person with Calypto CEO Sanjiv Kaul, an articulate and energetic spokesman for the company. We started with Cadence’s recent purchase of Forte Design Systems.

Kaul said, “Cadence bought Forte because high-level synthesis is going mainstream, and we think we are well positioned to take advantage of that. Integration between Catapult C [Calypto’s HLS synthesis tool, acquired from Mentor Graphics in 2011] and our Formal tool is what the market needs today.”

Asked if companies are still having to evangelize for Formal verification, Kaul said, “Formal is a big term for a lot of different technologies, but equivalence checking has been around for a long time, gate-to-gate, RTL-to-gate and RTL-to-RTL, and is widely deployed. Today equivalence checking is an integral part of most IC verification methodologies.

sanjiv_finalsm“One example is the wide-spread use of our sequential logic equivalence checking tool, SLEC Pro. Our power optimization product, PowerPro, takes RTL and creates power optimized RTL. Instead of having to run exhaustive simulations to verify that the functionality of the design has not changed, our customers can use SLEC Pro to automatically verify the correctness of the changes.

“Another product that we have been working on is an enhanced version of SLEC HLS. The purpose of this product is to independently confirm that the C++ or System C that Catapult synthesizes into RTL is equivalent. This is a tough challenge because Catapult can take in untimed C and the synthesized RTL is fully timed. Our PhD’s have been hard at work on this problem, and we feel that we have a unique understanding of the challenges and the solutions.”

Switching to tutorial mode, I asked Kaul to describe the major buckets within Formal.

He explained, “There is classic equivalence checking and then there’s property verification, like what Jasper does, which has always been a tough challenge. Jasper has done a good job in this area; just look at their website where they talk about specific applications and how their tools have been tuned for those apps.” [Since our conversation, Jasper has been acquired by Cadence.]

I asked if Calypto might expand into some of the other buckets in Formal.

Kaul said, “Verifying what Catapult does is tough enough. At present, we’re fully engaged with those challenges. However, there are other exciting things happening in the industry where we are involved.

“Power is becoming increasingly important and design teams often have to meet very tight power budgets. Today most power optimizations target static power at the gate and transistor level, but the possible power saving is small. That is why design teams are increasingly optimizing power at the RTL stage. With the increasing move to FinFET technology, dynamic power will dominate and dynamic power optimization at RTL is where Calypto’s PowerPro excels.

“The other exciting transition, as I said, is that high-level synthesis is going mainstream. One of the reasons driving this change is that RTL simulation is a major cost and bottleneck. When you move to C++ or System C, your simulations become hundreds of times faster.

“To leverage these savings in simulation time, a Formal solution to verify the equivalence of the C and the resulting RTL is imperative. We see the market moving strongly in this direction, and we are excited by this opportunity.”

Calypto’s got its eye on market trends. Does the market have an eye on Calypto?

Kaul answered, “We used to have two competitors in the HLS market, but now that Cadence has bought Forte, there’s just one. Forte’s tools and Cadence’s C-to-Silicon have significant overlap, however, so Cadence will have to find a way to leverage the strengths of both into something more powerful in a reasonable timeframe.

“We have, on the other hand, a very highly differentiated product strategy. We have Catapult, meeting both the SystemC and C++ challenge, plus we have our RTL power-optimization suite, PowerPro.”

Has Gary Smith’s predictions over these last many years finally been fulfilled, I asked, regarding system-level design because there are two dynamic players in high-level synthesis?

Kaul said, “Well, we agree with Cadence that high-level synthesis is going mainstream, even if there are only a few companies playing in the field. As we watch our business double and triple in size, we would say those insights are correct.

“But system-level design is more about modeling and co-design of hardware/software at higher levels of abstraction. High-level synthesis is more specific, and HLS tools cannot take just any C code and make it into RTL; it needs synthesizable C. Some system-level tools operate at that level, but many [operate in a larger niche].

“The market is still in its early stages, but companies are looking at all of this and inching towards an overall strategy that [addresses] high-level synthesis and system-level design. Customers are accepting that there is value in these tools, because their engineers are standing up and asking for them. As a result, we are having less and less trouble convincing customers to pay good money for good tools.”

I asked Kaul to make his own predictions regarding all of this: Where will we be in 5 years?

Kaul said, “Look at an SoC today – it is 50 percent memory, 25 percent pre-existing IP and processors, and 25 percent new design. It’s in some of those IP blocks where high-level synthesis is being used today.

“In just 5 years, all these new blocks will be done in high-level synthesis, more efficiently, with better quality, and lower verification costs. And, power analysis and optimization will have firmly moved to the RTL stage.”

This all sounds great, but can the vision actually be fulfilled?

Kaul responded emphatically, “I’m betting my career on it!”


At DAC 2014 …

Calypto Design Systems will be exhibiting in Booth #2333, Moscone Center in San Francisco in June, at the 51st Design Automation Conference.

Calypto’s booth is strategically placed on a corner of the Exhibit Hall with Mentor Graphics as a neighbor to the left and Cadence to the right. Calypto’s going to enjoy a lot of foot traffic at their booth. perhaps you should sign up in advance if you want their full attention!


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