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Sanjay Gangal
Sanjay Gangal
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.

TAKUMI Graphics IP Cores Reference Designs Available on S2C Prototyping Platform

 
July 2nd, 2012 by Sanjay Gangal

Article source: S2C

Prototype-Ready IP jump starts complex SoC Integration with 3D Graphics 

S2C announces that TAKUMI Corporation, a Japan-based advanced Graphics Intellectual Properties (IP) provider, has implemented a series of Graphics IP cores on S2C’s rapid FPGA-based prototyping systems including GS3000 and GSV3000 cores.  These TAKUMI IP cores have been fully validated in FPGAs and can be easily demonstrated to and evaluated by customers; thereby significantly reduce system-on-chip (SoC) integration time.

TAKUMI’s GSHARK family of IP is the graphics solution to accelerate display rendering on a variety of embedded systems including mobile devices, digital home appliances and in-car information systems. Uniquely designed and customized to support embedded systems, GSHARK-TAKUMI family extensively lines up graphics IP cores addressing different embedded system use models, for the best IP selection.

Toshio Nakama, S2C’s Chief Executive Officer, said,” Integrating a complex IP core, such as a 3D graphics IP, in a SoC design often requires tremendous amount of verification effort such as verifying the correctness of all hardware functions, evaluating SoC bus efficiency and testing software compatibilities.  And, the best methodology today for performing these tasks is by using FPGA-based prototypes that closely resemble the entire design operating at or close to actual speed, many months before actual silicon is available.  We are very pleased to work with TAKUMI to provide SoC developers a series of advanced graphics IP cores already mapped on FPGA-based prototypes that can significantly shorten IP integration into SoC design and allow early start of software development and testing.”

Read the rest of TAKUMI Graphics IP Cores Reference Designs Available on S2C Prototyping Platform

D68000 IP Core with Linux, MAC & debugger

 
June 28th, 2012 by Sanjay Gangal

Article source: Digital Core Design

Digital Core Design, IP Core and SoC design laboratories from Poland have introduced the newest version of the Motorola’s 68000 16/32-bit microprocessor. D68000 is the industry’s low cost 32-bit MCU, offering not only a low cost entry point but also effective performance. Improved architecture enables this IP Core to run with uCLinux, so it can be  easily used as HTTP server or FTP client.

The D68000 is 100% compatible with original Motorola’s 68000 and as a proof, just to mention, that a test run on classic Amiga 500+ computer showed clearly that DCD’s CPU can be 1:1 replacement for original chip. But classic computers are not the target destination for the product, cause improved architecture, creates new possibilities. D68000 runs with uCLinux Operating System, which makes this IP Core interesting solution for embedded servers, certified to be used only with m68k processors. The BOA application is used as HTTP server and effective communication could be established through FTP protocol. uCLinux is a MMU‐less derivative of Linux Operating System adopted for embedded solutions. It provides all of the Linux benefits including superior stability, Common Linux Kernel API, multitasking, full featured TCP/IP networking, Virtual File System and reduces the amount of memory needed by its kernel and running applications [it utilizes just 400kB].

Read the rest of D68000 IP Core with Linux, MAC & debugger

Cortus Launches APS3R 32 bit Microcontroller IP Core for Low Energy Embedded Applications

 
May 22nd, 2012 by Sanjay Gangal

Article source: Cortus

Cortus extends its family of 32 bit modern RISC microcontroller IP cores with the energy efficient APS3R. The APS3R is aimed at low power embedded applications such as wireless sensor networks, touchscreen controllers, smart cards and systems using energy harvesting.

Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the release of the latest member of their processor family: the energy efficient APS3R. The APS3R builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual core configuration is possible.

APS3R Dual Core

The Cortus APS3R is a 32-bit processor designed specifically for low power embedded systems featuring a 32-bit modern RISC architecture with sixteen 32-bit registers and a 5-7 stage pipeline. It is the second member of the Cortus microcontroller IP core family to be released in 2012 complementing the single precision floating point FPS6 core.

Read the rest of Cortus Launches APS3R 32 bit Microcontroller IP Core for Low Energy Embedded Applications

Hard IP, an introduction to increasing ROI for VLSI Chip designs

 
March 27th, 2012 by Graham Bell

I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at EDACafe.com.   With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on EDACafe.com.  Here below is a copy of the Preface to the book and introduces the material.  I hope you find it interesting and useful.

PREFACE

A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.

In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.

Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up! Read the rest of Hard IP, an introduction to increasing ROI for VLSI Chip designs

The Fastest USB 3.0 Performance in the Universe

 
March 23rd, 2012 by Graham Bell

Eric Huang demonstrates a Synopsys USB 3.0 Host, Device, and PHY IP running real USB 3.0 traffic at the fastest speeds ever recorded.

The demonstration runs on HAPS FPGA-Based Prototying platform (HAPS51) with a USB 3.0 xHCI Host on Windows 7 with MCCI drivers. The Device uses Linux to implement a mass storage design. It’s super fast, because we use a RAM disk (not an SSD or HDD) for storing the data so it shows the USB 3.0 Digital IP and PHYs can really move data. It’s the fastest USB IP in the universe according to Synopsys.

Algorithmic Memory Eases the Transition to Next-Generation Process Node

 
March 12th, 2012 by Graham Bell
Badawi Dweik, Director of Product Marketing, Memoir Systems discusses how new memory technology can ease the transition to the next generation silicon process node.

Next-generation performance means different things for different applications. For high performance computing, faster processor clock speeds may be the ticket. For mobile computing, energy efficiency is paramount. For feature-rich consumer electronics, size matters and packing more functionality into a smaller form factor is the order of the day. SoC architects use a wide variety of techniques to increase application performance. However, the ultimate route to breakthrough performance, by any measure, is next-generation semiconductor process technology. Many designers would like to take advantage of the latest process node technology, but are forced to wait 6 to 12 months until the memory IP portfolio is fully developed and validated for the new process node. A new memory technology called Algorithmic Memory® can greatly ease the burden of migration and enable a broad memory portfolio much earlier.

Fig. 1 Illustration of RTL Algorithmic IP enabling a multi-port memory.

Read the rest of Algorithmic Memory Eases the Transition to Next-Generation Process Node

Building a Successful Non Volatile Memory (NVM) Company on the basis of CMOS Oxide Breakdown

 
February 27th, 2012 by Graham Bell

The following article is by Ms. Linh Hong, vice president of marketing at Kilopass Technology, Santa Clara, CA, and first appeared in the Jan. 9 issue of EDA Weekly.

Starting its second decade in business under current CEO Charlie Cheng, Kilopass Technology Inc. continues its successful growth driven by two major movements. The first comprises market forces where consumers are demanding greater functionality from their mobile smart devices beyond audio and video to include environmental data that will eventually provide life care for the consumer. The second involves technology forces that continue to deliver more transistors per silicon area for each new semiconductor process generation, now at 28nm going to 20nm.

The widespread adoption of Kilopass’ unique standard logic CMOS anti-fuse, one-time programmable (OTP), non-volatile memory (NVM) intellectual property (IP) is reflected in the growing number of Kilopass foundry and IDM partners. Among foundries signing new agreements are UMC, SMIC, GLOBALFOUNDRIES, Dongbu and TowerJazz, that join long-standing Kilopass partner TSMC, the first to offer Kilopass IP at 28nm. The key to success for an IP company is silicon enablement and Kilopass IP is available on process nodes from 180nm down to 28nm at its major foundry partners to provide solutions to customers across many markets. Among major Integrated Device Manufacturers (IDMs) inking deals with Kilopass are the major suppliers of image sensors, display drivers, and gaming chips.

To understand how this successful start-up is being driven by evolutionary technical and market forces, an explanation of the company’s patented anti-fuse NVM IP and how it compares with alternative NVM solutions is the place to begin. Next, a description of how this anti-fuse NVM IP has symbiotically evolved with the steady progression of each new generation of standard logic CMOS processes, currently at 28nm and moving to 20nm and beyond, is in order. Finally, a discussion of how the anti-fuse NVM IP uniquely serves the four high-volume applications where it is being incorporated will detail how market forces are driving the company’s ongoing success.

Read the rest of Building a Successful Non Volatile Memory (NVM) Company on the basis of CMOS Oxide Breakdown

Non Volatile Memory IP for Analog and Mixed Signal Design

 
January 25th, 2012 by Graham Bell

This presentation “Non Volatile Memory IP for Analog and Mixed Signal Design” was presented at the TowerJazz Global Symposium, November 3rd at the TowerJazz headquarters in Newport Beach, California. The presenter is Bernd Stamme, Director of Marketing and Applications at Kilopass Technology Inc. in Santa Clara, California. His 20 minute presentation provides a comparison of various non-volatile memory IP (intellectual property) blocks that can be used on an integrated circuit to contain data that must be preserved when power is removed. This information might include user identification, secure codes for accessing digital rights management and others.

Cosmic Circuit’s Custom ASICs for Sensor Front Ends

 
January 11th, 2012 by Graham Bell
The January Cosmic Rays newsletter from Cosmic Circuits detailed the issues for creating custom ASICs for sensor front ends.  The article is shown here:

Custom ASICs are often deployed in sensor read-out electronics. These read-out systems tend to be unique and require the custom ASIC to

  • realize the unique functions at the power dissipation suitable for the system,
  • reduce cost and
  • protect intellectual property.

This article walks through the key elements of a custom solution for a Sensor Front End.

Successful Sensor Front Ends usually consist of the following key elements in realizing a complete solution

  1. Robust architectural definition
  2. Sensor interface electronics – often a preamplifier or instrumentation amplifier

ADC

  1. Sensor excitation circuits
  2. Calibration and Production support
Architecting the solution
Some of the key architectural decisions need to be made early in the architecture phase – these include AC or DC excitation of the sensor, , observation time of the sensor signal, voltage definition if battery operated and communication mechanism from sensor to digital processing engine.

Cosmic Circuits engineers work with customers through this phase to define an optimal solution after weighing feasibility of IC implementation.

 

Read the rest of Cosmic Circuit’s Custom ASICs for Sensor Front Ends

Video Presentation on Arasan Total IP Solutions

 
December 14th, 2011 by Graham Bell

Arasan Total IP Solutions

Arasan Chip Systems’ mobile connectivity products provide system architects and SoC design teams with silicon-proven, validated IP that helps ensure the integration and verification of digital, analog and software components in the shortest possible time with the lowest risk. These IP solutions have been incorporated into millions of mobile devices, including smartphones, tablets, digital cameras, portable game consoles, and many others.

Arasan’s high-quality Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers traffic generators, software stacks and drivers, and optional customization services for MIPI, USB, SD, SDIO, MMC/ eMMC, CF, UFS and many other popular standards.

Prakash Kamath, VP of Engineering for Arasan Chip Systems explains Total IP Solutions in this video:


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