Open side-bar Menu
 IP Showcase

Archive for November, 2016

REUSE 2016: Addressing the Four Freedoms

Thursday, November 24th, 2016

 


On Thursday next week
, December 1st, the IP community is going to launch its own IP-centric conference, REUSE 2016. It’s an important moment: Can the conference live up to its potential, provide a unique venue for discussions of this critical technology niche, and offer something to the diverse IP industry that they would not find elsewhere – all bundled together in one conference?

There are four major issues that haunt the IP industry, four freedoms demanded by the diverse, global customer base that buys from the IP industry. If REUSE 2016 wants to become the forum for those who provide IP to those customers, all four of these issues need to be addressed on December 1st in one way or another.

(more…)

Ridgetop Group & BaySand: Whole greater than Sum of Parts

Thursday, November 17th, 2016

 


Ridgetop Group
, a complex company based in Tucson, announced a “wide-ranging” partnership with San Jose-based BaySand to “leverage their complementary skills” and offer to SoC developers in Silicon Valley and Asia “design expertise and FPGA-to-ASIC conversion for mass production using Ridgetop Group technology.”

Together the companies say they will “work cooperatively to develop a series of new applications to increase their existing mixed-signal IP portfolios.”

Considering the growing emphasis on IP in the semiconductor supply chain, this news is of particular interest. The implication being IP companies need to provide design services to succeed. Ridgetop Group is an IP company, BaySand a design company. Together they provide what the market needs, good IP and design services tailored exactly to the system integration profile of a particular class of IP.

(more…)

DAC 2017: Deadlines for IP Submissions start November 15th

Thursday, November 10th, 2016

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

(more…)

REUSE 2016: Glamor Touches IP, at last

Thursday, November 3rd, 2016

 


Check out the link to know
that the upcoming conference, REUSE 2016, will be something to behold. Slated for Thursday, December 1st, at the Computer History Museum, the event website is glamorous and the promise of the show profound:

“REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world-famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.”

(more…)

Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy