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Archive for April, 2016

ESD Alliance: Lanza and Semico to serve as Change Agents

Wednesday, April 20th, 2016


The ESD Alliance has announced two additional updates
on its remarkable road to renaissance. The Alliance formerly known as the EDA Consortium says Dr. Lucio Lanza, long-time EDA investor and 2014 Kaufman Award winner, is joining the organization’s board of directors, effective immediately.

That news is unique for 4 reasons: a) Lanza is the first new board member since EDAC was relaunched as ESDA; b) Lanza is the only member of the board who is not currently serving as the CEO of a company, the first such circumstance in recent memory; c) Lanza serves on the board of PDF Solutions, triggering another first in that one company is now represented twice on the EDAC/ESDA board with PDF’s John Kibarian also serving therein; and d) Lanza was not elected, but appointed.

Certainly for all of these reasons and more, Dr. Lucio Lanza will serve as a refreshing change agent as the EDA Consortium morphs into the ESD Alliance.

The second major update from the ESD Alliance is the announcement of a “cooperative marketing” partnership with Semico.


IP @ DAC: Sound & Fury or Smoke & Mirrors

Thursday, April 14th, 2016


IP now dominates design automation
, evidenced in no small measure by ARM’s seat at the head of the table for the ESD Alliance, ESDA being an important sponsor of the Design Automation Conference. Everyone seems to agree that IP reuse is the only way complex mega-systems of the 21st century can be designed, so not surprisingly the DAC program now reflects that reality. There are sessions every day categorized as being IP-related, but are those designations accurate?

I would argue that a lot of the content that’s sitting in the IP Track at DAC is really just about design, and not specifically about IP-based design. To prove that point, below is a complete listing of the sessions in the IP Track that’s set to air between June 6th and 9th at DAC in Austin. Those that are legitimately about IP are bolded, sessions that actually talk about using IP. Those not bolded are ‘just’ about design, or are merely high-level nattering about superficial issues associated with IP reuse.

Conclusion: the number of IP-related sessions are far fewer than one would hope. If IP is this important, why aren’t there more sessions that are really about IP? Is there a conspiracy here?

Fortunately, this next week I’m talking at length with Warren Savage. As CEO of IPextreme, his knowledge about the technology and business of IP is pretty encyclopedic. I will run my conspiracy theory past him: DAC wants you to believe they believe in IP, but in fact the conference is still more about design automation, not about using silicon IP to enhance the process. EDA vendors still rule the roost at DAC.


SNPS’ Custom Compiler: closing the FinFET productivity gap

Thursday, April 7th, 2016


Synopsys Marketing Director and long-time EDA contributor Dave Reed
 talked recently about the company’s new, highly anticipated product release, Custom Compiler.

“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”

Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”

There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.

“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.


S2C: FPGA Base prototyping- Download white paper

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