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Archive for July, 2013

Money matters: It’s an IP, IP, IP, IP World

Thursday, July 25th, 2013


Fifty years ago, you would have known that it was a Mad, Mad, Mad, Mad World. Today, however, it’s an IP, IP, IP, IP World. Should you choose to cling to any skepticism about this state of affairs, here’s how to get over it.

Below you’ll find a very rough set of numbers [gleaned from Yahoo Financials] that look at the stock valuations of four companies that Play Large in the world of EDA and IP.  You’ll see posted there, a compare/contrast of the corporate performances of Mentor Graphics, Synopsys, Cadence, and ARM over the last 1 year, 2 years, and 5 years.

Remember back to the summer of 2008? The sky was falling, the world’s economy was  hell-bent on reaching the brink of cataclysmic collapse, and although Cadence was aggressively going after Mentor Graphics, the company was in truth only a handful of weeks away from a complete collapse of its own, the dismembering of the executive team in mid-October 2008.  Given the drama of that time, could we have predicted where we would be today?


5S: The Kaizen of SIP

Thursday, July 18th, 2013


We are all familiar with the 5S mantra for running a tightly choreographed manufacturing operation. It’s an intuitively pleasing and simplified set of rules for improving and maintaining physical plants, and can be targeted at everything from making cars to creating an effective commercial lab space. The ideas behind Sort, Straighten, Scrub, Standardize, and Sustain are closely linked to the writings of just-in-time efficiency expert Hiroyuki Hirano, and are also often associated with the term Kaizen.

Taking into consideration the admirable characteristics of Kaizen, is it possible to contemplate a 5S program for using semiconductor IP in a lean and efficient way? Although any number of S’s might fill the bill, let’s consider Seek, Sort, Satisfy, Stitch, and Sell as one such assembly of terms that could guide the IP user.


S2C: FPGA Base prototyping- Download white paper

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