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Archive for March 27th, 2012

Hard IP, an introduction to increasing ROI for VLSI Chip designs

Tuesday, March 27th, 2012

I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at EDACafe.com.   With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on EDACafe.com.  Here below is a copy of the Preface to the book and introduces the material.  I hope you find it interesting and useful.

PREFACE

A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.

In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.

Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up! (more…)

NEC: CyberWorkbench
S2C: FPGA Base prototyping- Download white paper



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