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Archive for March, 2012

Hard IP, an introduction to increasing ROI for VLSI Chip designs

Tuesday, March 27th, 2012

I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at   With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on  Here below is a copy of the Preface to the book and introduces the material.  I hope you find it interesting and useful.


A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.

In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.

Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up! (more…)

The Fastest USB 3.0 Performance in the Universe

Friday, March 23rd, 2012

Eric Huang demonstrates a Synopsys USB 3.0 Host, Device, and PHY IP running real USB 3.0 traffic at the fastest speeds ever recorded.

The demonstration runs on HAPS FPGA-Based Prototying platform (HAPS51) with a USB 3.0 xHCI Host on Windows 7 with MCCI drivers. The Device uses Linux to implement a mass storage design. It’s super fast, because we use a RAM disk (not an SSD or HDD) for storing the data so it shows the USB 3.0 Digital IP and PHYs can really move data. It’s the fastest USB IP in the universe according to Synopsys.

Algorithmic Memory Eases the Transition to Next-Generation Process Node

Monday, March 12th, 2012
Badawi Dweik, Director of Product Marketing, Memoir Systems discusses how new memory technology can ease the transition to the next generation silicon process node.

Next-generation performance means different things for different applications. For high performance computing, faster processor clock speeds may be the ticket. For mobile computing, energy efficiency is paramount. For feature-rich consumer electronics, size matters and packing more functionality into a smaller form factor is the order of the day. SoC architects use a wide variety of techniques to increase application performance. However, the ultimate route to breakthrough performance, by any measure, is next-generation semiconductor process technology. Many designers would like to take advantage of the latest process node technology, but are forced to wait 6 to 12 months until the memory IP portfolio is fully developed and validated for the new process node. A new memory technology called Algorithmic Memory® can greatly ease the burden of migration and enable a broad memory portfolio much earlier.

Fig. 1 Illustration of RTL Algorithmic IP enabling a multi-port memory.


S2C: FPGA Base prototyping- Download white paper
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