Archive for the ‘Uncategorized’ Category
Thursday, November 17th, 2016
Ridgetop Group, a complex company based in Tucson, announced a “wide-ranging” partnership with San Jose-based BaySand to “leverage their complementary skills” and offer to SoC developers in Silicon Valley and Asia “design expertise and FPGA-to-ASIC conversion for mass production using Ridgetop Group technology.”
Together the companies say they will “work cooperatively to develop a series of new applications to increase their existing mixed-signal IP portfolios.”
Considering the growing emphasis on IP in the semiconductor supply chain, this news is of particular interest. The implication being IP companies need to provide design services to succeed. Ridgetop Group is an IP company, BaySand a design company. Together they provide what the market needs, good IP and design services tailored exactly to the system integration profile of a particular class of IP.
Thursday, November 10th, 2016
Next Tuesday, November 15th, is the deadline for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.
[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]
In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.
The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.
Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.
So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?
Thursday, November 3rd, 2016
Check out the link to know that the upcoming conference, REUSE 2016, will be something to behold. Slated for Thursday, December 1st, at the Computer History Museum, the event website is glamorous and the promise of the show profound:
“REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world-famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.”
Thursday, October 27th, 2016
Raise your hand if you think innovation comes out of small, nimble, edgy startups. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.
Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.
Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.
However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.
Thursday, October 13th, 2016
Next week, DVCon is once again in Europe, October 19-20 in Munich. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.
It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.
Thursday, September 22nd, 2016
Geoff Tate, founding CEO at Rambus, is busy – again. These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.
When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.
“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”
“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”
Thursday, September 15th, 2016
Synopsys has a problem. Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.
Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.
Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.
In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.
Thursday, September 8th, 2016
Over the last several weeks, the ESD Alliance has announced two more members, news of particular interest because both companies are IP vendors. C-Sky Microsystems provides 32-bit embedded CPU cores, and Silvaco provides EDA tools for development of analog/mixed-signal devices, power IC and memory design.
True, Silvaco doesn’t sound like an IP vendor until you remember that it just acquired IPextreme, a well-known player in the IP market headed up by Warren Savage. And Savage, now GM of Silvaco’s IP Division, has recently been named chair of the ESD Alliance Semiconductor IP Working Group, tasked with developing a common methodology, best practices for fingerprinting, and solutions for tracking and auditing IP.
Meanwhile, C-Sky Microsystems brings its own unique value proposition to ESD Alliance. Described in the Press Release as “the first IP company from China to join the ESD Alliance,” C-Sky says it intends to actively participate in Savages’ SIP Working Group. This second bit is admirable, but the first could prove complicated.
Thursday, August 25th, 2016
This week’s blog post is authored by Bill Finch, Senior VP at CAST, Inc., long-time provider of IP cores and platform IP products. The discussion below maps the evolution of technologies and strategies that produced today’s IoT to the critical road map needed to achieve tomorrow’s.
IoT: The Second Coming
The second wave of the IoT is about to start. In the first wave, there was little clarity about what functionality really mattered. Engineers were tasked with getting products out ASAP. Because of the uncertainty and rush, most first-wave products were built around off-the-shelf parts made by IDMs (Integrated Device Manufacturers). The emphasis was on getting things working, not on optimization.
This will not be true in the second wave.
Thursday, August 18th, 2016
This is Part 1 of a 5-part discussion of the International Workshop on Design Automation for Cyber-Physical Systems co-located with the Design Automation Conference in Austin in June. Attending this all-day event on Sunday, June 5th, required a commitment of 9 hours and a $200 registration fee, albeit it came with a generous box lunch.
Over the course of the day, 10 speakers expounded on everything from complexity to reliability, from resilience to resource management, from smart buildings to smart grids to smart cars, and threw in a large dollop, as well, of how to deal with those miscreants among us who see opportunities in the emerging world of CPS to do small, medium, and large amounts of harm to our fellow humans and institutions.
Now it’s true, the thought leaders who spoke at CPSDA were consistently articulate, intelligent and well-informed. Nonetheless – even after 9 hours of intense listening, and quite a bit of caffeine – I was still not exactly sure what a cyber-physical system is. So let’s be creative and make up our own definition.