Over the last several months, Synopsys has made multiple announcements aggressively proving their ongoing presence in the burgeoning IP market: Silicon IP, Verification IP, and ARM-based design. Meanwhile, through community outreach, Synopsys has also continued to enhance the most important category of intellectual property: students in local schools.
Chris Rowen is Founder and CTO of Tensilica, an IP company based in Silicon Valley. We spoke last week by phone to discuss how an IP company decides what and when to introduce new products.
I first asked to Chris for a brief history of the RISC [Reduced Instruction Set Computing] architecture he is closely associated with, and how that history segued into the founding of Tensilica.
From RISC to Tensilica …
Q: Can you give me a quick overview of the origins of RISC architecture?
Chris Rowen: RISC is a set of ideas that grew up in academia and IBM in response to increased architectures in both the mainframe and microprocessor worlds.
People saw machines with really high hardware costs being built for assembly [language applications]. However, as compiler technology got better, people said: If I want a compiler to run well, I don’t need fancy instructions. I only need a common set of instructions that run really fast. All other complex operations could be composed by the compiler out of these fast, simple operations.
RISC grew out of these compiler technology advances, and a recognition in the VLSI era that there was an opportunity to rethink the process of how the architecture could be put together. (more…)
Hal Barbour is President of CAST, an IP company based on the East Coast. Hal has a tremendous ability to explain the many facets of the industry, and it was a great pleasure to sit down and talk with him this week. When we spoke by phone on August 29th, he had just wrapped up an earlier call with a customer.
************************** Hal Barbour on All things IP …
Q: How do you make yourself known to customers?
Hal Barbour: We have always put a lot of information in the hands of our customers, but the delivery mechanism today is quite a bit different. We’ve learned to leverage most of the contemporary tools – blogs, online meetings, webinars, shows and press releases. Press releases are just as important as ever, but where we used to send them to a central distribution center and a group of editors, now there are about 15 or 20 various people and outlets who disseminate the information to a much larger population.
Q: And how do working engineers hear about the products?
Hal Barbour: That’s the really interesting thing. Engineers today can easily see press releases directly, plus they have at their disposal a powerful set of search tools to help them get the information they need, so whatever information you’re putting out there, it better be right and it better be credible. If it’s not, engineers have got plenty of other sources to turn to.
And if you’re going to be out there, you better be able to respond to inquiries quickly and rapidly. Ultimately, however, it’s your name and your reputation that sells products. I can’t tell you the number of people who contact us based on our name and reputation.
Q: Isn’t that called ‘word of mouth’?
Hal Barbour: That’s exactly what it is, only it’s even faster today. Spreading the word used to be limited by who you knew, but today with social media and blogs, word of mouth moves at lighting speed and is more important than ever. Even today, though, nothing substitutes for face-to-face contact with the customer.
Behind Warren Savage’s calm and courteous demeanor beats the heart of a revolutionary: A guy who not only talks the talk, but walks the walk of growing his beloved IP industry through the most radical of ideas – cooperation.
Warren is the founder and CEO of IPextreme, a Silicon-Valley based company helping other companies commercialize their IP, small nuggets of pure gold that would otherwise enjoy only internal use. With the assist of Warren & Co, that gold is beefed up, intensely documented, and then licensed to users outside the firewall who then have access to robust 3rd-party design blocks, yielding revenue back to the IP developers they would not otherwise enjoy.
So that’s Warren’s business, but what’s really impressive about Warren is the other half of his professional involvement: working through the GSA [Global Semiconductor Alliance] to enhance the well-being of all players in the IP industry, not just his customers. Warren chairs GSA’s Working Group on IP, and leads the Leadership Group subset within that Working Group.
Warren also founded and continues to lead Constellations, a consortium-like group of IP vendors who meet regularly to discuss business issues, develop joint solutions, and host invitation-only events for their customers. The next Constellations event is coming up in early October.
Clearly, Warren Savage is a revolutionary, someone who believes a rising tide raises all boats in the IP industry and acts vigorously on that belief. Warren and I spoke by phone on August 22nd.
I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at EDACafe.com. With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on EDACafe.com. Here below is a copy of the Preface to the book and introduces the material. I hope you find it interesting and useful.
A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.
In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.
Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up! (more…)
Eric Huang demonstrates a Synopsys USB 3.0 Host, Device, and PHY IP running real USB 3.0 traffic at the fastest speeds ever recorded.
The demonstration runs on HAPS FPGA-Based Prototying platform (HAPS51) with a USB 3.0 xHCI Host on Windows 7 with MCCI drivers. The Device uses Linux to implement a mass storage design. It’s super fast, because we use a RAM disk (not an SSD or HDD) for storing the data so it shows the USB 3.0 Digital IP and PHYs can really move data. It’s the fastest USB IP in the universe according to Synopsys.
The following article is by Ms.Linh Hong, vice president of marketing at Kilopass Technology, Santa Clara, CA, and first appeared in the Jan. 9 issue of EDA Weekly.
Starting its second decade in business under current CEO Charlie Cheng, Kilopass Technology Inc. continues its successful growth driven by two major movements. The first comprises market forces where consumers are demanding greater functionality from their mobile smart devices beyond audio and video to include environmental data that will eventually provide life care for the consumer. The second involves technology forces that continue to deliver more transistors per silicon area for each new semiconductor process generation, now at 28nm going to 20nm.
The widespread adoption of Kilopass’ unique standard logic CMOS anti-fuse, one-time programmable (OTP), non-volatile memory (NVM) intellectual property (IP) is reflected in the growing number of Kilopass foundry and IDM partners. Among foundries signing new agreements are UMC, SMIC, GLOBALFOUNDRIES, Dongbu and TowerJazz, that join long-standing Kilopass partner TSMC, the first to offer Kilopass IP at 28nm. The key to success for an IP company is silicon enablement and Kilopass IP is available on process nodes from 180nm down to 28nm at its major foundry partners to provide solutions to customers across many markets. Among major Integrated Device Manufacturers (IDMs) inking deals with Kilopass are the major suppliers of image sensors, display drivers, and gaming chips.
To understand how this successful start-up is being driven by evolutionary technical and market forces, an explanation of the company’s patented anti-fuse NVM IP and how it compares with alternative NVM solutions is the place to begin. Next, a description of how this anti-fuse NVM IP has symbiotically evolved with the steady progression of each new generation of standard logic CMOS processes, currently at 28nm and moving to 20nm and beyond, is in order. Finally, a discussion of how the anti-fuse NVM IP uniquely serves the four high-volume applications where it is being incorporated will detail how market forces are driving the company’s ongoing success.
The January Cosmic Rays newsletter from Cosmic Circuits detailed the issues for creating custom ASICs for sensor front ends. The article is shown here:
Custom ASICs are often deployed in sensor read-out electronics. These read-out systems tend to be unique and require the custom ASIC to
realize the unique functions at the power dissipation suitable for the system,
reduce cost and
protect intellectual property.
This article walks through the key elements of a custom solution for a Sensor Front End.
Successful Sensor Front Ends usually consist of the following key elements in realizing a complete solution
Robust architectural definition
Sensor interface electronics – often a preamplifier or instrumentation amplifier
Sensor excitation circuits
Calibration and Production support
Architecting the solution
Some of the key architectural decisions need to be made early in the architecture phase – these include AC or DC excitation of the sensor, , observation time of the sensor signal, voltage definition if battery operated and communication mechanism from sensor to digital processing engine.
Cosmic Circuits engineers work with customers through this phase to define an optimal solution after weighing feasibility of IC implementation.
Arasan Chip Systems’ mobile connectivity products provide system architects and SoC design teams with silicon-proven, validated IP that helps ensure the integration and verification of digital, analog and software components in the shortest possible time with the lowest risk. These IP solutions have been incorporated into millions of mobile devices, including smartphones, tablets, digital cameras, portable game consoles, and many others.
Arasan’s high-quality Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers traffic generators, software stacks and drivers, and optional customization services for MIPI, USB, SD, SDIO, MMC/ eMMC, CF, UFS and many other popular standards.
Prakash Kamath, VP of Engineering for Arasan Chip Systems explains Total IP Solutions in this video:
As the last quarter unfolded, it became clear that the semiconductor market continues to lag amid the global economic and political concerns around the world. The events continue to unfold and despite progress on various fronts, lingering concerns still inject caution into the overall outlook. To navigate this turbulence, Open-Silicon has maintained a focused on its core beliefs: customer-centric solutions, operational excellence and customer satisfaction. With those in mind let’s review recent developments at the company.
First of all, throughout 2011 our customers increasingly asked us for ARM®-based solutions, in both mobile and non-traditional ARM markets. In response, this summer we greatly expanded our relationship with ARM, becoming one of a few companies worldwide offering ARM-based ASIC design services backed with a comprehensive multi-year ARM licensing agreement. And we did not stop there – to further integrate ARM processors, graphics and system IP into a complete solutions package, we created the ARM Center of Excellence. Open-Silicon’s ARM Center of Excellence builds upon our foundation of ASIC design and manufacturing by adding SoC architecture and transaction-level modeling, system prototyping, ARM-based software, and board design services to complete the solutions offering.
Another recent trend has been growing demand for our Interlaken Controller IP, which is helping core networking infrastructure devices achieve the next level of performance. However, increased performance has highlighted the challenge in another area: memory bandwidth. Our customers increasingly also need solutions to address memory interface bandwidth, especially in packet-processing and high-performance computing systems. In response, this October Open-Silicon joined DRAM leaders Micron and Samsung in the new Hybrid Memory Cube (HMC) Consortium. As a founder and developer member of the Consortium, Open-Silicon will help ASIC and ASSP developers access the revolutionary HMC technology through a combination of industry standards development, HMC interface IP, and HMC-specific design services.
HMC, leveraging Through-Silicon Via (TSV) technology and state-of-the-art DRAM design, promises to bring unparalleled bandwidth (over 15X better than DDR3), footprint savings (90% less space), and major power savings compared to DDR-based solutions. I believe HMC will enable new solutions in networking, cloud computing and high-bandwidth applications, which are currently not possible due to constraints in processor-memory interfaces.
In the coming quarter, Open-Silicon plans to expand its team and add capabilities to go deeper into system-level solutions and hardware-software design. In addition to our conventional capabilities with ASICs, we strongly believe that with our focus on system-level solutions, ARM-based SoCs and differentiated memory solutions, we will continue bringing significant value to our customers.