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Money matters: It’s an IP, IP, IP, IP World

Thursday, July 25th, 2013


Fifty years ago, you would have known that it was a Mad, Mad, Mad, Mad World. Today, however, it’s an IP, IP, IP, IP World. Should you choose to cling to any skepticism about this state of affairs, here’s how to get over it.

Below you’ll find a very rough set of numbers [gleaned from Yahoo Financials] that look at the stock valuations of four companies that Play Large in the world of EDA and IP.  You’ll see posted there, a compare/contrast of the corporate performances of Mentor Graphics, Synopsys, Cadence, and ARM over the last 1 year, 2 years, and 5 years.

Remember back to the summer of 2008? The sky was falling, the world’s economy was  hell-bent on reaching the brink of cataclysmic collapse, and although Cadence was aggressively going after Mentor Graphics, the company was in truth only a handful of weeks away from a complete collapse of its own, the dismembering of the executive team in mid-October 2008.  Given the drama of that time, could we have predicted where we would be today?


5S: The Kaizen of SIP

Thursday, July 18th, 2013


We are all familiar with the 5S mantra for running a tightly choreographed manufacturing operation. It’s an intuitively pleasing and simplified set of rules for improving and maintaining physical plants, and can be targeted at everything from making cars to creating an effective commercial lab space. The ideas behind Sort, Straighten, Scrub, Standardize, and Sustain are closely linked to the writings of just-in-time efficiency expert Hiroyuki Hirano, and are also often associated with the term Kaizen.

Taking into consideration the admirable characteristics of Kaizen, is it possible to contemplate a 5S program for using semiconductor IP in a lean and efficient way? Although any number of S’s might fill the bill, let’s consider Seek, Sort, Satisfy, Stitch, and Sell as one such assembly of terms that could guide the IP user.


Update: IP on the move

Thursday, June 20th, 2013


Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.

Synopsys and OCZ Technology Group announced OCZ “achieved first-pass silicon success” in its newest NAND flash Vector SSD using Synopsys’ DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System, and Professional Services.

The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”


Freescale’s Nunez: Get it in writing before integrating External IP

Wednesday, June 12th, 2013


Freescale IP Design Manager Jose Nunez presented a tutorial on Tuesday, June 4th, at the Design Automation Conference in Austin entitled “Challenges of Integrating External IP”.  Through a show of hands, he found the majority of his audience were IP users and therefore knew his comments would be of more than passing interest.

Nunez first noted there are even challenges in reusing internally-generated IP – big companies often have multiple groups, each with different ways and methodologies for designing IP blocks. He said, however, his talk would focus on licensing third-party IP – standard IP such as PCI Express and USB, which would add no value to Freescale if developed internally, as well as other types of IP, which if developed internally might exceed a need-by date. In such cases, he said, licensing third-party IP almost always proves cheaper in the long run, but it has to be done with care!

Nunez cited common misconceptions: 1) When companies use widely-available third-party IP from known providers, it means those blocks come with fewer bugs. 2) If everybody’s using third-party IP, it can’t be that hard to integrate it into a project. 3) Third-party IP always delivers best-in-class features, maturity, power and speed.  Having set the stage, he then listed some straightforward guidelines for interfacing with IP vendors, and using their products.


DAC 2013: IP news in advance of Austin

Thursday, May 30th, 2013


** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits.


Kanai Ghosh: A singular effort that changes the conversation

Thursday, May 9th, 2013


There’s a guy working away in Bangalore today who would like to change your ideas about what you pay for EDA tools. His name is Kanai Ghosh and his tool suite is called edautils, as in EDA Utilities. I spoke with Kanai on Skype recently about his efforts.

He told me that after a number of years working in EDA and CAD tool development, he decided to design his own suite of tools. Now several years into that process, working nights and weekends in and around his day job, Kanai’s tools are available for free download on his website.

Per Kanai, edautils pays particular attention to problems associated with integrating IP into larger SoC projects – a critical problem, he says, because today’s design projects can include more than 250 pieces of IP. In addition, today’s SoC has “multiple power and voltage domains” which the designer has to deal with by changing the design on the fly as the design constraints evolve, the designer constantly making “tradeoffs between power/performance/area and the project budget.”


Bill Martin: clarifying Accellera’s IP Tagging 1.0 Standard

Tuesday, April 30th, 2013


Bill Martin, President/VP of Engineering at E-System Design, sent a thoughtful response to my April 25th blog regarding Accellera’s recently released Soft IP Tagging 1.0 standard. I appreciate the time he took to clarify the ongoing need for such a standard.


I was part of VSIA when Kathy Werner was driving the IP tagging standards. I am happy this one from Accellera is now out [Soft IP Tagging 1.0] and the various users can determine how best to apply it. It is a large step forward, but only one of many required.

Unfortunately, the current system for IP tagging can be easily ‘hacked’ to disable any tracking. Simple text editing the source code and removing a few lines can completely remove the tag. But Accellera’s standard is a good first step to hone the standard; understanding how it works and does not work for various constituents.


IP Tagging 1.0 standard: Holy Grail or TMI?

Thursday, April 25th, 2013


Here’s a rhetorical question regarding Accellera Systems Initiative’s newly announced Soft IP Tagging 1.0 Standard: Is this the holy grail of IP or simply way too much information?

The question seems a fair one given the description in Accellera’s April 15th Press Release: “Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track ‘where used’ for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data.”

This last bit, the part where bug fixes can be applied, is clearly the stuff of holy grails. But that first bit – reversing the “normal” loss of control regarding the source of third-party IP after it’s licensed and unlocked – isn’t the stuff of TMI, too much information revealed about something that may be better off kept under wraps?


SIP: And in other news …

Thursday, April 11th, 2013


Years ago, an editor/mentor advised me never to cover legal battles between companies in this industry. He’d always say, “There’s no good to be had from covering this stuff. The story’s always so much more complicated than anybody every fesses up to, so just don’t go there.”

So, how about this? Shall we accentuate the positive and decentuate the negative? You think that’s stupid, naive, not gritty enough? Well, y’all know where to go if you want to accentuate the negative and decentuate the positive. Y’all know where to go if you want the rumors and innuendo.

If, however, you’d rather start off your week with something a bit more upbeat, stick around.


IP @ DAC: a session a day keeps the doctor away

Thursday, April 4th, 2013


Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars.

Here’s your DAC planning guide …


DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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