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Hal Barbour: Master of the mega-trend

Thursday, August 30th, 2012

 

Hal Barbour is President of CAST, an IP company based on the East Coast. Hal has a tremendous ability to explain the many facets of the industry, and it was a great pleasure to sit down and talk with him this week. When we spoke by phone on August 29th, he had just wrapped up an earlier call with a customer.

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Hal Barbour on All things IP …

Q: How do you make yourself known to customers?

Hal Barbour: We have always put a lot of information in the hands of our customers, but the delivery mechanism today is quite a bit different. We’ve learned to leverage most of the contemporary tools – blogs, online meetings, webinars, shows and press releases. Press releases are just as important as ever, but where we used to send them to a central distribution center and a group of editors, now there are about 15 or 20 various people and outlets who disseminate the information to a much larger population.

Q: And how do working engineers hear about the products?

Hal Barbour: That’s the really interesting thing. Engineers today can easily see press releases directly, plus they have at their disposal a powerful set of search tools to help them get the information they need, so whatever information you’re putting out there, it better be right and it better be credible. If it’s not, engineers have got plenty of other sources to turn to.

And if you’re going to be out there, you better be able to respond to inquiries quickly and rapidly. Ultimately, however, it’s your name and your reputation that sells products. I can’t tell you the number of people who contact us based on our name and reputation.

Q: Isn’t that called ‘word of mouth’?

Hal Barbour: That’s exactly what it is, only it’s even faster today. Spreading the word used to be limited by who you knew, but today with social media and blogs, word of mouth moves at lighting speed and is more important than ever. Even today, though, nothing substitutes for face-to-face contact with the customer.

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Warren Savage: the revolutionary in our midst

Thursday, August 23rd, 2012

 

Behind Warren Savage’s calm and courteous demeanor beats the heart of a revolutionary: A guy who not only talks the talk, but walks the walk of growing his beloved IP industry through the most radical of ideas – cooperation.

Warren is the founder and CEO of IPextreme, a Silicon-Valley based company helping other companies commercialize their IP, small nuggets of pure gold that would otherwise enjoy only internal use. With the assist of Warren & Co, that gold is beefed up, intensely documented, and then licensed to users outside the firewall who then have access to robust 3rd-party design blocks, yielding revenue back to the IP developers they would not otherwise enjoy.

So that’s Warren’s business, but what’s really impressive about Warren is the other half of his professional involvement: working through the GSA [Global Semiconductor Alliance] to enhance the well-being of all players in the IP industry, not just his customers. Warren chairs GSA’s Working Group on IP, and leads the Leadership Group subset within that Working Group.

Warren also founded and continues to lead Constellations, a consortium-like group of IP vendors who meet regularly to discuss business issues, develop joint solutions, and host invitation-only events for their customers. The next Constellations event is coming up in early October.

Clearly, Warren Savage is a revolutionary, someone who believes a rising tide raises all boats in the IP industry and acts vigorously on that belief. Warren and I spoke by phone on August 22nd.

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Hard IP, an introduction to increasing ROI for VLSI Chip designs

Tuesday, March 27th, 2012

I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at EDACafe.com.   With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on EDACafe.com.  Here below is a copy of the Preface to the book and introduces the material.  I hope you find it interesting and useful.

PREFACE

A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.

In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.

Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up! (more…)

The Fastest USB 3.0 Performance in the Universe

Friday, March 23rd, 2012

Eric Huang demonstrates a Synopsys USB 3.0 Host, Device, and PHY IP running real USB 3.0 traffic at the fastest speeds ever recorded.

The demonstration runs on HAPS FPGA-Based Prototying platform (HAPS51) with a USB 3.0 xHCI Host on Windows 7 with MCCI drivers. The Device uses Linux to implement a mass storage design. It’s super fast, because we use a RAM disk (not an SSD or HDD) for storing the data so it shows the USB 3.0 Digital IP and PHYs can really move data. It’s the fastest USB IP in the universe according to Synopsys.

Building a Successful Non Volatile Memory (NVM) Company on the basis of CMOS Oxide Breakdown

Monday, February 27th, 2012

The following article is by Ms. Linh Hong, vice president of marketing at Kilopass Technology, Santa Clara, CA, and first appeared in the Jan. 9 issue of EDA Weekly.

Starting its second decade in business under current CEO Charlie Cheng, Kilopass Technology Inc. continues its successful growth driven by two major movements. The first comprises market forces where consumers are demanding greater functionality from their mobile smart devices beyond audio and video to include environmental data that will eventually provide life care for the consumer. The second involves technology forces that continue to deliver more transistors per silicon area for each new semiconductor process generation, now at 28nm going to 20nm.

The widespread adoption of Kilopass’ unique standard logic CMOS anti-fuse, one-time programmable (OTP), non-volatile memory (NVM) intellectual property (IP) is reflected in the growing number of Kilopass foundry and IDM partners. Among foundries signing new agreements are UMC, SMIC, GLOBALFOUNDRIES, Dongbu and TowerJazz, that join long-standing Kilopass partner TSMC, the first to offer Kilopass IP at 28nm. The key to success for an IP company is silicon enablement and Kilopass IP is available on process nodes from 180nm down to 28nm at its major foundry partners to provide solutions to customers across many markets. Among major Integrated Device Manufacturers (IDMs) inking deals with Kilopass are the major suppliers of image sensors, display drivers, and gaming chips.

To understand how this successful start-up is being driven by evolutionary technical and market forces, an explanation of the company’s patented anti-fuse NVM IP and how it compares with alternative NVM solutions is the place to begin. Next, a description of how this anti-fuse NVM IP has symbiotically evolved with the steady progression of each new generation of standard logic CMOS processes, currently at 28nm and moving to 20nm and beyond, is in order. Finally, a discussion of how the anti-fuse NVM IP uniquely serves the four high-volume applications where it is being incorporated will detail how market forces are driving the company’s ongoing success.

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Cosmic Circuit’s Custom ASICs for Sensor Front Ends

Wednesday, January 11th, 2012
The January Cosmic Rays newsletter from Cosmic Circuits detailed the issues for creating custom ASICs for sensor front ends.  The article is shown here:

Custom ASICs are often deployed in sensor read-out electronics. These read-out systems tend to be unique and require the custom ASIC to

  • realize the unique functions at the power dissipation suitable for the system,
  • reduce cost and
  • protect intellectual property.

This article walks through the key elements of a custom solution for a Sensor Front End.

Successful Sensor Front Ends usually consist of the following key elements in realizing a complete solution

  1. Robust architectural definition
  2. Sensor interface electronics – often a preamplifier or instrumentation amplifier

ADC

  1. Sensor excitation circuits
  2. Calibration and Production support
Architecting the solution
Some of the key architectural decisions need to be made early in the architecture phase – these include AC or DC excitation of the sensor, , observation time of the sensor signal, voltage definition if battery operated and communication mechanism from sensor to digital processing engine.

Cosmic Circuits engineers work with customers through this phase to define an optimal solution after weighing feasibility of IC implementation.

 

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Video Presentation on Arasan Total IP Solutions

Wednesday, December 14th, 2011

Arasan Total IP Solutions

Arasan Chip Systems’ mobile connectivity products provide system architects and SoC design teams with silicon-proven, validated IP that helps ensure the integration and verification of digital, analog and software components in the shortest possible time with the lowest risk. These IP solutions have been incorporated into millions of mobile devices, including smartphones, tablets, digital cameras, portable game consoles, and many others.

Arasan’s high-quality Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers traffic generators, software stacks and drivers, and optional customization services for MIPI, USB, SD, SDIO, MMC/ eMMC, CF, UFS and many other popular standards.

Prakash Kamath, VP of Engineering for Arasan Chip Systems explains Total IP Solutions in this video:


YouTube Direkt

Open-Silicon Fall 2011 Update by Dr. Naveed Sherwani, Co-Founder, President & CEO

Tuesday, December 6th, 2011

 

 

 

 

 

 

 

 

As the last quarter unfolded, it became clear that the semiconductor market continues to lag amid the global economic and political concerns around the world. The events continue to unfold and despite progress on various fronts, lingering concerns still inject caution into the overall outlook. To navigate this turbulence, Open-Silicon has maintained a focused on its core beliefs: customer-centric solutions, operational excellence and customer satisfaction. With those in mind let’s review recent developments at the company.

First of all, throughout 2011 our customers increasingly asked us for ARM®-based solutions, in both mobile and non-traditional ARM markets. In response, this summer we greatly expanded our relationship with ARM, becoming one of a few companies worldwide offering ARM-based ASIC design services backed with a comprehensive multi-year ARM licensing agreement. And we did not stop there – to further integrate ARM processors, graphics and system IP into a complete solutions package, we created the ARM Center of Excellence. Open-Silicon’s ARM Center of Excellence builds upon our foundation of ASIC design and manufacturing by adding SoC architecture and transaction-level modeling, system prototyping, ARM-based software, and board design services to complete the solutions offering.

Another recent trend has been growing demand for our Interlaken Controller IP, which is helping core networking infrastructure devices achieve the next level of performance. However, increased performance has highlighted the challenge in another area: memory bandwidth. Our customers increasingly also need solutions to address memory interface bandwidth, especially in packet-processing and high-performance computing systems. In response, this October Open-Silicon joined DRAM leaders Micron and Samsung in the new Hybrid Memory Cube (HMC) Consortium. As a founder and developer member of the Consortium, Open-Silicon will help ASIC and ASSP developers access the revolutionary HMC technology through a combination of industry standards development, HMC interface IP, and HMC-specific design services.

HMC, leveraging Through-Silicon Via (TSV) technology and state-of-the-art DRAM design, promises to bring unparalleled bandwidth (over 15X better than DDR3), footprint savings (90% less space), and major power savings compared to DDR-based solutions. I believe HMC will enable new solutions in networking, cloud computing and high-bandwidth applications, which are currently not possible due to constraints in processor-memory interfaces.

In the coming quarter, Open-Silicon plans to expand its team and add capabilities to go deeper into system-level solutions and hardware-software design. In addition to our conventional capabilities with ASICs, we strongly believe that with our focus on system-level solutions, ARM-based SoCs and differentiated memory solutions, we will continue bringing significant value to our customers.

 

Mystified About MIPI? Let Us MIPIfy You! – Part 3

Monday, November 21st, 2011

Jump to Part 1

Jump to Part 2

When it comes to selecting IP, the biggest concerns of design engineers are interoperability (will IP from one vendor work with IP from another), ease of integration, and the quality and reliability of the resulting system.

So who should you turn to for your MIPI IP? The answer is Arasan (www.arasan.com), which provides a total MIPI IP solution. We are deep domain experts who have been with the MIPI Alliance since its inception and who were the first to demonstrate working MIPI solutions. All of the MIPI board members are our customers, as are many of the 200+ contributing members.

Figure 3. Arasan offers a total MIPI IP solution.

As a simple example, consider the CSI-2 and DSI interfaces shown in Figure 1. Some IP vendors supply the CSI-2 transmitter, some supply the CSI-2 receiver and a few supply both; similarly for the DSI device and host controllers. But no single IP vendor has all of these cores… except for Arasan.

Actually, the real-world situation is even more complex, because some IP vendors supply only the digital portions of the IP, leaving their customers to source the D-PHY IP from another vendor. In fact, some IP vendors supply only the D-PHY and/or M-PHY, but have no deep understanding with regard to the digital portions of the interfaces. The problem is that, as was noted in the discussions associated with Figure 1, the digital IP blocks communicate with the D-PHY using the PPI (PHY Protocol Interface), but this interface is only optional and is subject to interpretation; suffice it to say that the end result may not be pretty.

Arasan can supply both the digital IP and the analog PHY for any existing MIPI standard, including CSI-2, DSI, SLIMbus, and HSI, along with the D-PHY and M-PHY. But there’s more to IP than RTL (for the digital portions) and GSDII (for the analog blocks). When we say that Arasan provides a total MIPI IP solution, we mean that we supply RTL (GDSII where applicable), ESL (Behavioral) and Transaction-Level Models (TLMs), Verification IP (VIP), software drivers and stacks, reference designs, and full hardware development kits (HDKs) and platforms.

And, as domain experts, in addition to the MIPI IP itself, we also offer consultation services with regard to alternative architectural scenarios such as the optimum number of lanes to use for a particular application. Furthermore, we provide unparalleled support direct from the engineers who develop our IP, which means you simply cannot ask our engineers something about the IP that they don’t know.

Another consideration is the quality of the verification IP (VIP) that accompanies the main IP cores. IP vendors typically create both the IP cores and the corresponding VIP. One potential problem is that the interface specifications aren’t always 100% comprehensive. The result is that it’s possible to introduce a non-standard interpretation of a corner case condition (possibly even a full-up error) into the IP and to then create VIP that tests for the incorrect implementation.In order to address this issue, although we create and ship our own VIP, we use VIP from other leading vendors to double-check our IP.

Summary

The MIPI suite of interfaces – coupled with the D-PHY and M-PHY physical layers – help designers of mobile and consumer products to reduce cost, complexity, power consumption, and EMI while increasing bandwidth and performance. MIPI addresses all of the subsystems found in mobile and consumer products, including graphics (cameras and displays), audio, radio, control, storage, and power management.

Arasan can supply a total MIPI IP solution for any existing MIPI standard, including digital IP, analog/PHY IP, verification IP (VIP), software stacks and drivers, hardware development kits, and… the list goes on. In addition to offering consultation services with regard to alternative architectural scenarios and customization, Arasan also provides unparalleled support direct from the engineers who develop our IP.

We are deep domain experts who have been with the MIPI Alliance since its inception and who were the first to demonstrate working MIPI solutions. All of the MIPI board members are our customers, as are many of the 200+ contributing members. The quality of our total MIPI IP solution, coupled with the fact that Arasan can supply a total MIPI IP solution for any existing MIPI standard, explains why Arasan is the MIPI IP vendor of choice. Call Arasan today and let us MIPIfy you!

Please visit www.mipi.org for further information on MIPI in general.

Please visit www.arasan.com for further information on Arasan’s total MIPI IP solutions.

**  End of Article **

Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.

 

**  End of Part 2 **

Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.

Mystified About MIPI? Let Us MIPIfy You! – Part 2

Wednesday, November 9th, 2011

Jump to Part 1

CSI-2, DSI, and the D-PHY

There are so many aspects to MIPI that it can be difficult for newcomers to take everything in, so let’s start with the Camera Serial Interface (CSI) and the Display Serial Interface (DSI). Currently in deployment, CSI-2 and DSI each require a maximum of six signals depending on the number of lanes used by the designer. Also, as illustrated in Figure 1, CSI-2 and DSI both share a common PHY (physical interface) known as the D-PHY, which is designed so as to offer high-speed with low power consumption and low EMI.

 

 

 

 

 

 

 

 

 

Figure 1. A high-level view of a product utilizing CSI-2 and DSI.

In particular, observe the way in which the PHY Protocol Interface (PPI) is used to communicate between the D-PHY and the higher-level protocols. We will return this interface later in this article when we come to discuss the various things design teams have to consider when selecting MIPI IP from different IP vendors.

It’s important to note that different systems may perform processing tasks in different ways. Consider the camera sensor, for example. Some sensors deliver their captured data raw directly to the application processor/SoC, leaving it to perform any required post-processing. Other camera sensors may pre-process the captured data and then hand the result over to the application processor/SoC. The CSI-2 interface can handle all such use cases.

Also of interest is the fact that even though they transport data in a serialized form, both CSI-2 and DSI maintain any real-time information associated with the data stream; for example the DSI will include event data such as V-Sync and H-Sync information.

Two other MIPI standards that are currently in deployment and that deserve mention are SLIMbus (Serial Low-power Inter-chip Media Bus) and HSI (High-speed Synchronous Serial Interface). SLIMbus is a low-power, low-speed peripheral bus that supports multiple clock/sample rates and is used to handle things like control signals and audio channels. SLIMbus can be used to replace existing I2C and I2S interfaces while offering more features and requiring the same or less power than the two combined. Meanwhile, HSI is a general-purpose interface that offers intermediate bandwidth capabilities between SLIMbus and the CSI-2 and DSI interfaces.

 

Emerging M-PHY-based MIPI Protocols

As discussed above, the original MIPI physical layer was the D-PHY, but the industry is starting to transition to a next-generation physical layer called the M-PHY. Both of these PHYs offer either high-speed or low-power signaling. The M-PHY uses fewer pins, but offers more options and flexibility and faster signaling, scaling up to 6 GB/sec. In the same way that CSI-2 and DSI conceptually “ride on top” of the D-PHY, a variety of high-level protocols share the M-PHY as illustrated in Figure 2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2. A high-level view of emerging M-PHY-based protocols.

The Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile and consumer electronic systems. It is applicable to a wide range of component types including application processors, co-processors, and modems, as well as different types of data traffic including control messages, bulk data transfer, and packetized streaming.

The UFS (Universal Flash Storage) interface provides a simple standard interface aimed at the non-volatile memories (NVMs) that are used in mobile and consumer devices.UFS is a JEDEC standard that uses MIPI standards as a subset for the lower level protocols.

The CSI-3 and DSI-2 protocols are the next-generation versions of the currently deployed CSI-2 and DSI protocols, respectively. These new versions support the higher bandwidths and resolutions that will be required by emerging products, including 3D cameras and displays.

Also of interest is the LLI (Low Latency Interface), which provides low latency chip-to-chip communications. Meanwhile, the low-power, high-speed DigRFv4 interface can be used to link the application processor/SoC to the baseband IC and the baseband IC to the RF IC.  Furthermore, the SSIC (SuperSpeedInterChip) specification, which is being developed in collaboration between the USB 3.0 group and the MIPI Alliance, will provide USB 3.0 speeds with fewer pins and less power, and will also allow reuse of existing USB drivers (this interface is currently under definition).

MIPI is Poised for Exponential Growth

Although the MIPI Alliance was formed eight years ago at the time of this writing, defining standards of this level of sophistication requires substantial amounts of time and effort. Thus, the works of the MIPI Alliance have only recently begun to come to fruition. However, in the same way that a snowball rolling downhill gathers size and momentum, the “MIPI snowball” has now started to roll!

According to IP Nest (www.ip-nest.com), MIPI is expected to reach 100% penetration in smartphones by 2013. And MIPI is no longer of interest only in the mobile market. MIPI has the potential to become the standard across the whole consumer product domain – anywhere where there’s a processor and a bunch of peripheral devices. In fact, according to InStat (www.instat.com), MIPI will have achieved 70% penetration in all forms of electronic consumer and computing devices by 2016.

**  End of Part 2 **

Jump to Part 3

Prakash Kamath is the Vice President of Engineering at Arasan Chip Systems (www.arasan.com). Responsible for almost 200 engineers worldwide, Prakash has 29 years of extensive Design and Management experience. Prakash has successfully contributed to establishing Arasan’s “Total IP Solution” and has been instrumental in achieving Arasan’s leadership position with regard to Solid-State Storage and MIPI IP solutions. Prior to joining Arasan in 2002, Prakash has held several design and management positions in companies like AMD, National, and Chips & Technologies. Prakash holds a BS degree from the University of Madras, India, and an MS degree from the University of California, Santa Barbara, USA.

 

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