Archive for the ‘Uncategorized’ Category
Thursday, August 31st, 2017
Between now and the end of 2017, it’s my hope to speak to every company currently a member of the ESD Alliance. These companies vary in size, interests, product offerings, and leadership outlooks. The one thing they share, however, is a sense that together they enhance the ecosystem within which electronic systems are designed.
Over the last several months, I’ve had the opportunity to speak with several companies in the ecosystem about Grand Challenges in IP and EDA – Sonics, CAST, Silvaco, Synopsys, Adapt-IP, and Mentor Graphics.
Now the plan is to speak with companies that are specifically members of the ESD Alliance with the following questions in mind:
Thursday, August 24th, 2017
Last month it was a visit to Thomas Alva Edison’s labs and manufacturing headquarters in West Orange, New Jersey, and this month it was a 20-hour road trip to see the eclipse in rural Oregon, accompanied by a books-on-tape rendition of “The Wright Brothers” by David McCullough. These two things together – the visit and the road trip – brought into sharp focus the historical impact of the patent process on innovation and technology in the U.S.
Edison had only a grade-school education, yet his inventiveness and fierce sense of competition drove him to create not only world-changing technologies on his own, but to establish a revolutionary full-fledged R&D facility in West Orange [moved from its original location in Menlo Park] and the means by which ideas emanating from those labs could be commercialized and ramped to volume manufacturing. He wanted to own the entire process, from invention to final sale, and in many areas of science and engineering he did just that.
The Thomas Edison National Park is really just a series of wooden buildings where breakthroughs in the electric light bulb, and subsequent establishment of a power-distribution industry, as well as ground-breaking developments in recording sound, in particular the human voice, were pursued in lock-step with equally revolutionary developments in motion picture engineering. In fact, it was on this day in 1891 that Edison patented the Kinetograph, his term for a motion picture camera.
Thursday, August 3rd, 2017
As national and international news crashes over the shore, wave after wave, it’s easy to lose track of any particular item amidst the churning foam. The story discussed here, however, floats more visibly atop the flotsam and jetsam because it’s relevant to the IP and EDA industries.
Several weeks ago, Siemens AG – a German company – was caught-up in a violation of a part of the current EU sanctions against Russia. Siemens’s power turbines, having been sold to Russia – which was not a violation – were then allegedly modified and shipped off to Crimea for installation there – which was a violation.
You remember Crimea. It was part of Ukraine until 2014, and then it was not.
Anyway when the turbine situation was uncovered, the EU was not happy with Siemens; Siemens was not happy with Russia; if Russia or Crimea were unhappy with anyone, they kept it to themselves.
As a result of these revelations, Siemens AG now faces a fine from the EU, and has canceled several high-profile, lucrative business deals with Russian firms. Siemens is mad – slightly less rich, and mad.
Which brings us to Mentor Graphics. Such experts we are, who have had the chance to learn about Export Controls from the likes of Cadence’s Larry Disenhof or SmartFlow’s Ted Miracco, and it’s that knowledge which seems relevant to Mentor.
Wednesday, July 26th, 2017
It’s good to know another EDA startup has emerged, they’ve been in such short supply of late.
Austin-based Austemper Design Systems is an EDA startup focused on functional safety that had the good luck to find the Design Automation Conference in their own front yard this year – making it easy for the company to exhibit in Austin and showcase their newly announced suite of tools.
Speaking by phone in a recent call, Austemper Founder & CEO Sanjay Pillay said, “We offer four different tools in our suite, one that analyzes quantitative metrics, two for design automation that go in and add diagnostic conversions and can be used for a single block of IP or for the entire design, and a fourth tool that runs fault-injection analysis.”
Given that the company has only been underway since March 2015, I suggested that tool portfolio represents a lot of productivity over a short amount of time.
Pillay agreed: “Although we are young, we are already working with the largest semiconductor companies in the world, and in the process of negotiating licenses with others.
“DAC was a great place to announce our products. We had more than 30 meetings and demonstrations with potential customers and partners during DAC. It was also an opportunity for us to meet in person with people we have interacted with over e-mails and conference calls, to make that human connection.”
Thursday, July 20th, 2017
Last year, Texas-based Concertal Systems came to DAC, but only as an observer. This year, the 15-month-old startup actually exhibited at the conference and, per reports, gave a pitch-perfect debut of their newly announced offerings: A suite of web-based tools – Audition, Orchestrate, Rehearse – which the company says effectively solves many of the problems associated with SDA, system design automation.
Per Concertal Founder and CEO Bob Ledzius, the automation of modern system design is completely dependent on the ability to seek out, vet, and integrate IP. But that process has been stalled, until now.
“A lot of people have been promising these capabilities,” Ledzius said during our recent phone call, “but we’re actually delivering on the promise with our SDA methodology.
“A lot of people have been doing great stuff to solve the incremental problems around system design, but we started by asking the right questions, not just the incremental ones. We took a step back and said, if you want the ability to develop designs in minutes – not months – then you need to develop a system for high-level IP reuse.
“Starting from this point of view, we came up with specific conclusions and solved the problem of IP verification and integration.”
Wednesday, July 12th, 2017
It’s been a year since two cataclysmic news bits hit the wires, the two stories not unrelated.
The UK decided to Brexit the EU on 23 June 2016, and ARM announced it had been sold to Tokyo-based SoftBank three weeks later, on 18 July 2016. For some, these developments would have been unthinkable up to the moment they unfolded, but now they’re both a reality.
Article 50 was triggered by the British PM on 29 March 2017, and the UK will no longer be in the EU as of March 2019.
ARM is no longer publicly traded, and although it was once the crown jewel of Britain’s technical portfolio, it is now a wholly owned Japanese enterprise. Or at least it was, until 7 March 2017 when SoftBank announced an even more astonishing bit of news.
Thursday, June 22nd, 2017
Below is a contributed op-ed piece from SmartFlow Compliance Solutions CEO Ted Miracco, and company AE Akshay Dhule.
I last spoke with Miracco in November 2015 when the company launched, offering tools and strategies to software companies who have lost product to theft and piracy. At the time, Synopsys was dealing with a publicly-acknowledged system breach, so that conversation with SmartFlow was particularly pertinent.
This current piece, however, is about export compliance, a topic also of intense interest to the EDA industry.
Cadence’s Larry Disenhof is the industry’s subject expert in this area. Having heard him speak numerous times, although the piece below ends with a plug for SmartFlow, Disenhoff would undoubtedly agree with an articulate reminder that export compliance is neither optional nor for the faint of heart.
The message is clear: If you’re running a software company, ignore these issues at your own peril.
Thursday, June 15th, 2017
UltraSoC is on a roll, having just wrapped up an energetic participation in the last month’s RISC-V conference in Shanghai, where UltraSoC CTO Gadge Panesar was a speaker. Additionally, the company is announcing “new funding, new investors, and new board members” – including UC Berkeley’s Alberto Sangiovanni-Vincentelli.
When I spoke this week with company CEO Rupert Baines, he started with Shanghai: “There is so much interest in RISC-V in China. The attendance there [exceeded] the headcount at the previous meetings at Google and MIT, although the numbers may be confusing as there were so many students at the Shanghai event.”
Asked if the RISC-V event would be in China again, Baines said, “I believe going forward there will be one conference in the U.S. each year, probably in Silicon Valley, and one international. Nvidia sponsored the latest one through their presence in Shanghai.”
Turning to UltraSoC, I asked about the company’s origin, market and competition.
Baines said, “We do semiconductor IP that solves a problem. The chips are so big and complicated today, understanding how they work – with lots of processors and lots of software interacting with each other and the real world – is incredibly difficult.
Thursday, June 8th, 2017
This is fourth in a 4-part series on Grand Challenges in IP. Previous dialogs featured Sonics CEO Grant Pierce, CAST-IP Board Chair Hal Barbour, and Silvaco IP Division GM Warren Savage. This final, lengthy conversation is with Synopsys co-CEO Aart de Geus, winner of the 2008 Phil Kaufman Award.
To say Aart de Geus is synonymous with Synopsys, an organization he’s led for over 30 years, is not an understatement. His entire professional zeitgeist is wrapped up in the company. Neither is it an understatement to say de Geus is always on-message, always on-point. The interview below is no exception.
Dr. de Geus’ vision of Grand Challenges in IP is informed by the daily, working realities of the needs of the customers that constitute the IP market, and an IP vendor’s evolving response to those needs. We spoke by phone on June 1st.
Thursday, June 1st, 2017
This is the third in a four-part series showcasing Grand Challenges in IP. The first two conversations were with Sonics CEO Grant Pierce, and CAST Board Chair Hal Barbour.
This week’s dialog is with Warren Savage, founder and CEO of IPextreme. The company was purchased by Silvaco in 2016, where Savage now serves as GM of the IP division.
Warren Savage has been an energetic leader in the IP community, working to get companies in the industry to link arms, address common concerns, and give greater visibility to the importance of their products in the global semiconductor supply chain.
When we spoke on May 24th, Savage began by addressing my question about protection for IP blocks as they move down the manufacturing chain