Archive for the ‘Uncategorized’ Category
Thursday, June 22nd, 2017
Below is a contributed op-ed piece from SmartFlow Compliance Solutions CEO Ted Miracco, and company AE Akshay Dhule.
I last spoke with Miracco in November 2015 when the company launched, offering tools and strategies to software companies who have lost product to theft and piracy. At the time, Synopsys was dealing with a publicly-acknowledged system breach, so that conversation with SmartFlow was particularly pertinent.
This current piece, however, is about export compliance, a topic also of intense interest to the EDA industry.
Cadence’s Larry Disenhof is the industry’s subject expert in this area. Having heard him speak numerous times, although the piece below ends with a plug for SmartFlow, Disenhoff would undoubtedly agree with an articulate reminder that export compliance is neither optional nor for the faint of heart.
The message is clear: If you’re running a software company, ignore these issues at your own peril.
Thursday, June 15th, 2017
UltraSoC is on a roll, having just wrapped up an energetic participation in the last month’s RISC-V conference in Shanghai, where UltraSoC CTO Gadge Panesar was a speaker. Additionally, the company is announcing “new funding, new investors, and new board members” – including UC Berkeley’s Alberto Sangiovanni-Vincentelli.
When I spoke this week with company CEO Rupert Baines, he started with Shanghai: “There is so much interest in RISC-V in China. The attendance there [exceeded] the headcount at the previous meetings at Google and MIT, although the numbers may be confusing as there were so many students at the Shanghai event.”
Asked if the RISC-V event would be in China again, Baines said, “I believe going forward there will be one conference in the U.S. each year, probably in Silicon Valley, and one international. Nvidia sponsored the latest one through their presence in Shanghai.”
Turning to UltraSoC, I asked about the company’s origin, market and competition.
Baines said, “We do semiconductor IP that solves a problem. The chips are so big and complicated today, understanding how they work – with lots of processors and lots of software interacting with each other and the real world – is incredibly difficult.
Thursday, June 8th, 2017
This is fourth in a 4-part series on Grand Challenges in IP. Previous dialogs featured Sonics CEO Grant Pierce, CAST-IP Board Chair Hal Barbour, and Silvaco IP Division GM Warren Savage. This final, lengthy conversation is with Synopsys co-CEO Aart de Geus, winner of the 2008 Phil Kaufman Award.
To say Aart de Geus is synonymous with Synopsys, an organization he’s led for over 30 years, is not an understatement. His entire professional zeitgeist is wrapped up in the company. Neither is it an understatement to say de Geus is always on-message, always on-point. The interview below is no exception.
Dr. de Geus’ vision of Grand Challenges in IP is informed by the daily, working realities of the needs of the customers that constitute the IP market, and an IP vendor’s evolving response to those needs. We spoke by phone on June 1st.
Thursday, June 1st, 2017
This is the third in a four-part series showcasing Grand Challenges in IP. The first two conversations were with Sonics CEO Grant Pierce, and CAST Board Chair Hal Barbour.
This week’s dialog is with Warren Savage, founder and CEO of IPextreme. The company was purchased by Silvaco in 2016, where Savage now serves as GM of the IP division.
Warren Savage has been an energetic leader in the IP community, working to get companies in the industry to link arms, address common concerns, and give greater visibility to the importance of their products in the global semiconductor supply chain.
When we spoke on May 24th, Savage began by addressing my question about protection for IP blocks as they move down the manufacturing chain
Thursday, May 25th, 2017
This conversation with Hal Barbour, Chairman at CAST IP, is the second of four dialogs about Grand Challenges in IP.
The first installment in the series, published last week, was a conversation with Sonics co-Founder and CEO Grant Pierce.
Pierce argues that today’s Grand Challenges in IP center around the complexities of delivering sub-systems and related technical expertise to customers, helping develop edge-node devices targeted at Machine Learning, and providing IP for myriad automotive systems – all while meeting demands for greater bandwidth and throughput, and astonishingly low power.
In this week’s installment in the series, Hal Barbour talks about a completely different set of Grand Challenges in IP – those related to the business issues surrounding the industry.
Thursday, May 18th, 2017
Here begins the first of four dialogs about Grand Challenges in IP. This first installment is a conversation with Sonics co-Founder and CEO Grant Pierce, who also currently serves as Chair of the ESD Alliance. We spoke by phone earlier this week.
Asked to enumerate the Grand Challenges in IP he sees today, Pierce began: “Having been in the industry for 20 years myself, I am surprised that we still have some challenges ahead of us. We have new entrants into the industry that are more focused at the system level, however, with customers coming in to interact with the IP guys directly to get their custom designs done.
“What I am seeing today, versus 20 years ago, is the emergence of Machine Learning. And that brings with it some technical challenges. On the one hand, they are very familiar – the age-old challenges about bandwidth and throughput – but on the other hand, they are also very new. Today’s applications are driving things together in a totally new way.
Thursday, May 4th, 2017
It’s not been pretty of late in the world of IP. Imagination’s valuation tanked when it was revealed in early April that the company might be losing Apple as a customer. Imagination says it’s going to fight this development, but a different ending to the story of David and Goliath comes to mind in that declaration.
Then this week, that same Imagination announced it was selling MIPS – a company it bought back in 2012 with great fanfare for [a mere] $60 million. [It’s true, MIPS’ patent portfolio was worth a lot more.]
Also this week, TSMC announced it is charging a former employee with IP theft: The former employee is alleged to have stolen manufacturing data from TSMC specifically related to Nvidia and AMD chip production, taken it across the Straights of Taiwan, and turned it over to his new employer in the PRC, HLMC.
Thursday, April 27th, 2017
Tom Alsop and the team at Accellera are elated: The UVM standard has been accepted by the IEEE as 1800.2 and congratulations are certainly in order.
The effort has consumed upwards of 10 years, and represents thousands of man-hours of effort, consultation, compromise, consensus building, rinse and repeat. Over and over until the final product was polished, presented and approved by the IEEE. Not an easy process by anybody’s estimation.
When we spoke by phone this week about the Accellera announcement, I asked Tom Alsop [Principal Engineer at Intel] how difficult the whole thing had actually been.
He chuckled slightly: “For us, it was fairly difficult.”
Thursday, April 20th, 2017
There’s two kinds of conversations when it comes to electrical systems and cars. One is about the power train and the other one is about the advanced driver-assistance system, ADAS. Distinct as they may be, both of these systems can benefit from the optimizations associated with design automation, and both of these systems today are mashed up against the complexities of using third-party IP.
Chips in cars today need to manage the power train, or they need to provide safety and security for the driver – but either way, they need to work perfectly every time, all the time, and in some pretty hellish conditions. It’s hot under the hood and the road today is unforgiving. So are the lawyers.
So what’s a third-party IP provider supposed to do? Turn tail and run? Never sell into the automotive market where litigation looms larger than a sandstorm in April on the Texas Panhandle? Or try to man-up and work with the automotive market to provide IP that fits well into the chips that such customers need?
Thursday, April 13th, 2017
Something eerie and inexplicable happened on Thursday evening, April 6th. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.
Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.
Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.
No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.
That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.