Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
May 26th, 2016 by Peggy Aycinena
On Sunday, June 5th, my two favorites are: The Workshop on Design Automation for Cyber-Physical Systems, and The Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-Oriented Environments. Both of these all-day events feature experts from academia and industry, most speaking for at least 30 minutes. The topics will be very technical and the schedules allow for detailed presentations. Of course, this doesn’t mean the other workshops on Sunday don’t have great merit, but the two I have identified look to be particularly rich opportunities for learning.
Sunday evening, for the first time, there will also be a 2-hour panel focused on Career Perspectives in EDA, a discussion sponsored by CEDA. Although many will be obliged to attend networking dinners on Sunday evening, or will still be busy setting up booths for Monday morning’s Exhibit Hall opening, attending this Career Panel seems an opportunity not to be missed, particularly as it will be moderated by the supremely knowledgeable Bill Joyner from SRC. Admittedly, this is not a technical session, but the implications for the industry are profound. [File under the heading: ‘Concern for an Aging Industry’]
May 19th, 2016 by Peggy Aycinena
New companies have joined the consortium, the newest member of the Board of Directors is not a CEO, a plethora of monthly panels have engaged the industry in thought-provoking discussions about innovation vis-à-vis commercial enterprise, a marketing deal has been struck with Semico, and the whole friggin’ organization has been re-branded as the ESD Alliance to reflect an intent to get more IP guys, more Embedded guys, and more Yet-to-be-identified guys into the alliance than just the traditional anchor tenants from EDA.
But none of this comes close to the potential impact of the latest disruptive idea that ESDA is proposing: The founding of a brand new working group that could very well redefine the whole semiconductor supply chain: The ESD Alliance System Scaling Working Group.
May 12th, 2016 by Peggy Aycinena
Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.
A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]
May 5th, 2016 by Peggy Aycinena
“I think the content’s very good this year,” Savage said in a recent phone call. “We’ve been working on the IP content at the DAC for 3 years, and continue to make progress. I would say the biggest thing [we struggle with] is insufficient time allocated for IP.
“In comparison to previous years, however, the IP and Design tracks have been merged and all put under the same track – something we recommended against, because design-related submissions generally are different from IP-related submissions.”
April 20th, 2016 by Peggy Aycinena
That news is unique for 4 reasons: a) Lanza is the first new board member since EDAC was relaunched as ESDA; b) Lanza is the only member of the board who is not currently serving as the CEO of a company, the first such circumstance in recent memory; c) Lanza serves on the board of PDF Solutions, triggering another first in that one company is now represented twice on the EDAC/ESDA board with PDF’s John Kibarian also serving therein; and d) Lanza was not elected, but appointed.
Certainly for all of these reasons and more, Dr. Lucio Lanza will serve as a refreshing change agent as the EDA Consortium morphs into the ESD Alliance.
The second major update from the ESD Alliance is the announcement of a “cooperative marketing” partnership with Semico.
April 14th, 2016 by Peggy Aycinena
I would argue that a lot of the content that’s sitting in the IP Track at DAC is really just about design, and not specifically about IP-based design. To prove that point, below is a complete listing of the sessions in the IP Track that’s set to air between June 6th and 9th at DAC in Austin. Those that are legitimately about IP are bolded, sessions that actually talk about using IP. Those not bolded are ‘just’ about design, or are merely high-level nattering about superficial issues associated with IP reuse.
Conclusion: the number of IP-related sessions are far fewer than one would hope. If IP is this important, why aren’t there more sessions that are really about IP? Is there a conspiracy here?
Fortunately, this next week I’m talking at length with Warren Savage. As CEO of IPextreme, his knowledge about the technology and business of IP is pretty encyclopedic. I will run my conspiracy theory past him: DAC wants you to believe they believe in IP, but in fact the conference is still more about design automation, not about using silicon IP to enhance the process. EDA vendors still rule the roost at DAC.
April 7th, 2016 by Peggy Aycinena
“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”
Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”
There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.
“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.
March 24th, 2016 by Peggy Aycinena
Here’s the quote from Rhines included in EDAC’s press release discussing their Market Statistics Service report for Q4_2015:
“After 23 consecutive quarters of growth, the EDA Industry revenues declined slightly in the fourth quarter, compared to a particularly strong Q4 2014. However, industry revenue increased 5 percent for calendar 2015 compared to 2014, and the semiconductor IP and services categories increased in Q4. Geographically, the Asia Pacific region continues to grow, while other regions saw modest declines this quarter.”
March 9th, 2016 by Peggy Aycinena
Lots of people have been pointing out for a long time that membership in the EDA Consortium includes some of the biggest names in IP, not to mention embedded software, so not reflecting that reality in the organization’s name is pretty nonsensical. In fact, two recent blogs here on EDACafe specifically address the issue.
The first one is titled: “Answer’s nope: Should EDA Consortium become IP Consortium?” [September 30, 2015].
In this blog, I asked Mentor Graphics CEO Wally Rhines: “Aren’t the IP companies on the verge of overshadowing the size and impact of the EDA companies in the EDA Consortium. So much so, it seems like it’s time to change the name to the IP Consortium.”
Rhines responded, “It will never be the case that it’s all EDA or all IP. In fact, IP revenue is only one-third the size of the market tracked by MSS today. The other two-thirds is traditional EDA.
“Even ARM — although their market cap is $20 billion — their revenue is just about the same as Mentor’s. The EDA industry is a long way from being dominated by the IP industry, plus we’re in a very prosperous period in EDA. We’ve got 22 nanometers, 14, 10, 7 all working at the same time, so we’re meeting customer demands at all of these nodes.”
Last September, Dr. Rhines appeared distinctly underwhelmed by the argument that it’s time to change the Consortium’s name.
February 25th, 2016 by Peggy Aycinena
* Veloce Deterministic ICE: Designed to overcome unpredictability in ICE environments by adding 100-percent visibility and repeatability for debug; provides access to other ‘virtual-based’ use models.
* Veloce DFT: Designed to accelerate DFT verification prior to tape-out to minimize the risk of catastrophic failure; significantly reduces run times when verifying designs after DFT insertion.
* Veloce FastPath: Designed to optimize emulation performance when verifying large multi-clock SoC designs by enabling faster model execution speed.