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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Apocalypse soon: RISC-V channels mammals after the Asteroid

 
January 19th, 2017 by Peggy Aycinena


At the ESD Alliance panel on the Cadence campus Wednesday night
, it was Vista Ventures’ Jim Hogan who suggested the little open-source processor architecture called RISC-V will prove itself to be a plucky survivor when looming market realities hit 800-pound proprietary vendors like ARM and Intel. Hogan suggested RISC-V is positioned to survive that pending apocalypse just like “the mammals after the asteroid.”

Pretty dramatic stuff.

Hence it should not have been surprising, at the end of the 75-minute discussion on stage between Jim Hogan and Microsemi’s Ted Speers and SiFive’s Yunsup Lee, that I raised my hand and asked why Simon Segars was not in the room. After all, Simon Segars is both CEO of ARM and a key member of the Board of the Alliance that organized the Hogan-Speers-Lee program – a program where the emerging RISC-V movement was described as poised to upend the primacy of ARM etc.

Hogan responded to my question without answering: “Look, ARM is challenging by serving the low-cost processor market. License fees, royalty fees – that is what ARM wants for their low-power edge-based device. I think it was Simon, for example, who started talking to The Street about his economic strategy. It’s not really about what the best technology is, but about the economics. This is what gets the traction, and ARM will respond in an economic way.”

“Yes,” Ted Speers added, “and Intel and Imagination will also respond.”

Read the rest of Apocalypse soon: RISC-V channels mammals after the Asteroid

RISC-V: ESD Alliance to showcase Situational Irony on Jan 18th

 
January 5th, 2017 by Peggy Aycinena


One of your New Year’s Resolutions
should be to further understand the philosophy, technology, and implications of the RISC-V movement. And there will be no better way to follow through on that resolution than to attend the upcoming ESD Alliance discussion on the topic.

In a nod to the best in situational irony, the Alliance is hosting an evening event in Silicon Valley on January 18th specifically to discuss this open source processor architecture, which per some has the potential to turn ARM’s market dominance on its ear.

Read the rest of RISC-V: ESD Alliance to showcase Situational Irony on Jan 18th

Flex Logic & TSMC: embedded FPGA cores on 16nm FinFETs

 
December 14th, 2016 by Peggy Aycinena


Flex Logic announced some astonishing news this week
– the completed design of a “high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions.”

In a phone call to discuss the announcement, Flex Logic CEO and Co-founder Geoff Tate was clearly ebullient: “Last August we were talking about TSMC’s 40-nanometer ULP, ultra low power, and now this week we’re talking about the first 16-nanometer finFET plus.

“This one, our EFLX 100, is like the one we announced at 40 nanometers – but at 16 nanometers it will run much faster!

“We’ve done extensive measurements [to confirm] for many applications that these cores will run at 1GHz or faster, even in worst-case temperature conditions.”

Read the rest of Flex Logic & TSMC: embedded FPGA cores on 16nm FinFETs

IP Design Challenge: efabless & X-FAB promote Ingenuity, February deadline

 
December 7th, 2016 by Peggy Aycinena


If you’re a designer looking for a rare opportunity to shine, look no further
. The folks at Erfurt-based X-FAB and Silicon Valley-based efabless hope to “further ingenuity” by extending a challenge to anyone in the world willing to accept it.

What they’re looking for are IP designs applicable to an ultra-low power voltage reference, and the companies are willing to make it worth your while.

If your design is one of the top three selected, you’ll receive a monetary award and your IP will be made available to a global customer base through both X-FAB’s IP web portal and efabless’ online marketplace.

Best of all – you’ll hold onto all rights for your submission.

Read the rest of IP Design Challenge: efabless & X-FAB promote Ingenuity, February deadline

REUSE 2016: Addressing the Four Freedoms

 
November 24th, 2016 by Peggy Aycinena


On Thursday next week
, December 1st, the IP community is going to launch its own IP-centric conference, REUSE 2016. It’s an important moment: Can the conference live up to its potential, provide a unique venue for discussions of this critical technology niche, and offer something to the diverse IP industry that they would not find elsewhere – all bundled together in one conference?

There are four major issues that haunt the IP industry, four freedoms demanded by the diverse, global customer base that buys from the IP industry. If REUSE 2016 wants to become the forum for those who provide IP to those customers, all four of these issues need to be addressed on December 1st in one way or another.

Read the rest of REUSE 2016: Addressing the Four Freedoms

Ridgetop Group & BaySand: Whole greater than Sum of Parts

 
November 17th, 2016 by Peggy Aycinena


Ridgetop Group
, a complex company based in Tucson, announced a “wide-ranging” partnership with San Jose-based BaySand to “leverage their complementary skills” and offer to SoC developers in Silicon Valley and Asia “design expertise and FPGA-to-ASIC conversion for mass production using Ridgetop Group technology.”

Together the companies say they will “work cooperatively to develop a series of new applications to increase their existing mixed-signal IP portfolios.”

Considering the growing emphasis on IP in the semiconductor supply chain, this news is of particular interest. The implication being IP companies need to provide design services to succeed. Ridgetop Group is an IP company, BaySand a design company. Together they provide what the market needs, good IP and design services tailored exactly to the system integration profile of a particular class of IP.

Read the rest of Ridgetop Group & BaySand: Whole greater than Sum of Parts

DAC 2017: Deadlines for IP Submissions start November 15th

 
November 10th, 2016 by Peggy Aycinena


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

Read the rest of DAC 2017: Deadlines for IP Submissions start November 15th

REUSE 2016: Glamor Touches IP, at last

 
November 3rd, 2016 by Peggy Aycinena


Check out the link to know
that the upcoming conference, REUSE 2016, will be something to behold. Slated for Thursday, December 1st, at the Computer History Museum, the event website is glamorous and the promise of the show profound:

“REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world-famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.”

Read the rest of REUSE 2016: Glamor Touches IP, at last

EDA Death Spiral: Qualcomm/NXP last nail in coffin

 
October 27th, 2016 by Peggy Aycinena


Raise your hand if you think innovation comes out of small, nimble, edgy startups
. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.

Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.

Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.

However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.

Read the rest of EDA Death Spiral: Qualcomm/NXP last nail in coffin

DVCon Munich: IP Integration, Automotive, Smart Cities, System Design

 
October 13th, 2016 by Peggy Aycinena


Next week, DVCon is once again in Europe, October 19-20 in Munich
. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.

It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.

Read the rest of DVCon Munich: IP Integration, Automotive, Smart Cities, System Design

NEC: CyberWorkbench
Verific: SystemVerilog & VHDL Parsers
DAC2017



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