Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
September 26th, 2013 by Peggy Aycinena
EDAC hosted an evening seminar last week that could have taught you everything your company needs to know to meet your Export Compliance requirements – an unbelievably labyrinthine set of rules, created and nurtured by various agencies of the U.S. Government, that are designed in part to prevent sensitive technical IP from falling into the hands of less-than-totally-friendly nation states.
If you weren’t there on September 18th, you were not alone. A surprisingly small number of people showed up for the seminar, although the speaker, Cadence Group Director for Export Compliance and Government Relations Larry Disenhof, is clearly a walking encyclopedia on this stuff, and although EDAC did a great job publicizing the event.
If you didn’t attend EDA & Export Compliance, it was probably for one of two reasons: Your team already knows everything they need to know in order to meet their export obligations, or your team is oblivious to the fact that these requirements are not optional; they’re obligatory and failure to comply can precipitate fines of $250,000 and up, loss of export privileges, cancellation of pending M&A’s, and even jail time.
August 29th, 2013 by Peggy Aycinena
Tezzaron Founder and CTO Bob Patti delivered a rousing keynote at the Silicon Valley Magma User Group meeting back in 2010, talking about his company’s 3D memory technology and how it offered a solution to the increased demands for on-chip capacity. I spoke to Patti following that speech, with details of the conversation posted here.
In the past 3 years, things have only gotten worse with respect to memory demands, so one might think Tezzaron’s solution is in even greater demand today. The problem, of course, is that Tezzaron Semiconductor is not the only company offering something that looks like ‘3D memory.’
In fact, 3 weeks ago at MemCon 2013 in Silicon Valley, I attended a keynote given by Micron Technology’s Mike Black singing the praises of his company’s Hybrid Memory Cube. Sitting in the audience, I tried to compare and contrast the Micron technology with what I believed to be the Tezzaron solution.
Happily, Tezzaron had a booth at MemCon, so it was possible to talk to somebody from the company about how they viewed Micron’s competing technology. Unfortunately, Tezzaron VP David Chapman was surrounded by a mob of interested people when I got to the booth, so I took his card and arranged to talk to him later about my many questions.
My number one question: Given the size of Micron and the ecosystem of partners they’ve assembled, the Hybrid Memory Cube Consortium, is Tezzaron winning the battle of technology superiority, but losing the war for market share?
Tezzaron’s Chapman was not offended by my question. Instead, he started by framing his answer with a description of current market needs and continued from there. The following is a transcript of his comments.
August 15th, 2013 by Peggy Aycinena
Late last month, Synopsys announced another important addition to their portfolio, the DesignWare Sensor IP Subsystem. Per the company, “The new IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.
“The hardware components [include] a power- and area-efficient DesignWare 32-bit ARC EM4 processor, digital peripherals such as I2C, SPI, ADC interface, and GPIO, and hardware accelerators for signal processing functions. The software components [include] a comprehensive library of digital signal functions utilized in higher-level applications such as analog and digital sensor fusion, and mathematical functions, filtering and interpolation. In addition, peripheral drivers ease integration of the I/O with the ARC EM processor.”
With announcements such as this, two questions come to mind: Why are companies like Synopsys still classified as EDA with some IP, and not IP with some EDA? And isn’t Synopsys setting itself up as competition for its customers by selling such a sophisticated chunk of IP?
I had a chance to speak by phone last week with Rich Collins, Marketing Manager for Synopsys’ IP Subsystems, who answered my second question with ease: “I don’t think so, because this [subsystem] is not a critical part of the SoC. Our customers are trying to achieve a higher order of functionality. It’s our value proposition that by using this subsystem, we save them months and months of design and verification effort. We help them get to market more quickly, we are not in competition with them.”
August 1st, 2013 by Peggy Aycinena
Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.
Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.
At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.
Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:
July 25th, 2013 by Peggy Aycinena
Fifty years ago, you would have known that it was a Mad, Mad, Mad, Mad World. Today, however, it’s an IP, IP, IP, IP World. Should you choose to cling to any skepticism about this state of affairs, here’s how to get over it.
Below you’ll find a very rough set of numbers [gleaned from Yahoo Financials] that look at the stock valuations of four companies that Play Large in the world of EDA and IP. You’ll see posted there, a compare/contrast of the corporate performances of Mentor Graphics, Synopsys, Cadence, and ARM over the last 1 year, 2 years, and 5 years.
Remember back to the summer of 2008? The sky was falling, the world’s economy was hell-bent on reaching the brink of cataclysmic collapse, and although Cadence was aggressively going after Mentor Graphics, the company was in truth only a handful of weeks away from a complete collapse of its own, the dismembering of the executive team in mid-October 2008. Given the drama of that time, could we have predicted where we would be today?
July 18th, 2013 by Peggy Aycinena
We are all familiar with the 5S mantra for running a tightly choreographed manufacturing operation. It’s an intuitively pleasing and simplified set of rules for improving and maintaining physical plants, and can be targeted at everything from making cars to creating an effective commercial lab space. The ideas behind Sort, Straighten, Scrub, Standardize, and Sustain are closely linked to the writings of just-in-time efficiency expert Hiroyuki Hirano, and are also often associated with the term Kaizen.
Taking into consideration the admirable characteristics of Kaizen, is it possible to contemplate a 5S program for using semiconductor IP in a lean and efficient way? Although any number of S’s might fill the bill, let’s consider Seek, Sort, Satisfy, Stitch, and Sell as one such assembly of terms that could guide the IP user.
June 20th, 2013 by Peggy Aycinena
Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.
The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”
May 30th, 2013 by Peggy Aycinena
** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits.
May 9th, 2013 by Peggy Aycinena
There’s a guy working away in Bangalore today who would like to change your ideas about what you pay for EDA tools. His name is Kanai Ghosh and his tool suite is called edautils, as in EDA Utilities. I spoke with Kanai on Skype recently about his efforts.
He told me that after a number of years working in EDA and CAD tool development, he decided to design his own suite of tools. Now several years into that process, working nights and weekends in and around his day job, Kanai’s tools are available for free download on his website.
Per Kanai, edautils pays particular attention to problems associated with integrating IP into larger SoC projects – a critical problem, he says, because today’s design projects can include more than 250 pieces of IP. In addition, today’s SoC has “multiple power and voltage domains” which the designer has to deal with by changing the design on the fly as the design constraints evolve, the designer constantly making “tradeoffs between power/performance/area and the project budget.”