June 9th, 2016 by Peggy Aycinena
When SRC’s Bill Joyner took the podium this past Sunday evening at the 53rd DAC in Austin, he did something that’s never been done before: Present a panel about careers that wasn’t part of a Workshop for Women in EDA.
Up until 7 o’clock on June 5, 2016, a conversation about career perspectives was such a non-technical topic, it could only be found in Marie Pistilli’s beloved workshop, a venue where work/life balance, Academia vs. Industry, and how to promote your brand within the organization were thoroughly discussed every year for 15 years at DAC.
Now IEEE’s Council on EDA, CEDA, has made the bold decision to pick up where Marie’s workshop left off, sponsoring this week’s event and broadening the audience and the appeal.
Joyner had four people on his panel, a generous two hours to hash out various universal questions, and enough of a sense of humor to offer to wear the necktie he’d brought with him to add gravitas, or not to wear the tie to appear hipster and cool. He quickly decided to go without the tie, and the ensuing conversation went something like this.
Read the rest of CEDA Panel: Covering new ground at DAC 2016
June 2nd, 2016 by Peggy Aycinena
The first thing to do on Wednesday at DAC 2016 in Austin is take in an hour of the Exhibit Hall. This is the last day for the booths, people are zippy in the morning like horses sensing the stable at the end of their journey, and conversations on the floor are still about the technology. By the end of the afternoon, it’ll be about wistful goodbyes and, “Will we even be here next year when DAC again returns to the Lone Star State?”
Then from 10:30 to noon genuflect to Academia and check out ‘Accelerated Simulation for Circuit Reliability and Stability’. With speakers from Texas A&M, USC, Brown, and Michigan Tech. If you attend, you’ll learn what the future holds for simulation: power supply stability, soft error in logic circuits, thermal noise in ultra-low voltage designs, and the sparsification of spectral graphs used in various design problems. Nobody from industry is speaking, so if you want to get in on the ground floor commercializing some of this stuff, sit in the front row.
Read the rest of DAC 2016: Til the Bagpipes Play
May 26th, 2016 by Peggy Aycinena
There are clearly a lot of collateral distractions at the Design Automation Conference: Networking. Social Hours. Parties. Chotzkies. But the real fun at DAC comes from carving time out to attend technical sessions. This is year in Austin, the offerings are particularly rich.
On Sunday, June 5th, my two favorites are: The Workshop on Design Automation for Cyber-Physical Systems, and The Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-Oriented Environments. Both of these all-day events feature experts from academia and industry, most speaking for at least 30 minutes. The topics will be very technical and the schedules allow for detailed presentations. Of course, this doesn’t mean the other workshops on Sunday don’t have great merit, but the two I have identified look to be particularly rich opportunities for learning.
Sunday evening, for the first time, there will also be a 2-hour panel focused on Career Perspectives in EDA, a discussion sponsored by CEDA. Although many will be obliged to attend networking dinners on Sunday evening, or will still be busy setting up booths for Monday morning’s Exhibit Hall opening, attending this Career Panel seems an opportunity not to be missed, particularly as it will be moderated by the supremely knowledgeable Bill Joyner from SRC. Admittedly, this is not a technical session, but the implications for the industry are profound. [File under the heading: ‘Concern for an Aging Industry’]
Read the rest of Life is Short: Carpe Eruditio at DAC 2016
May 19th, 2016 by Peggy Aycinena
It’s a poorly kept secret that Bob Smith was brought in as Executive Director of EDAC last year to shake things up, to breathe new life into the sails of a somewhat becalmed organization. Well, in the category of be careful what you ask for, here’s how things have gone so far:
New companies have joined the consortium, the newest member of the Board of Directors is not a CEO, a plethora of monthly panels have engaged the industry in thought-provoking discussions about innovation vis-à-vis commercial enterprise, a marketing deal has been struck with Semico, and the whole friggin’ organization has been re-branded as the ESD Alliance to reflect an intent to get more IP guys, more Embedded guys, and more Yet-to-be-identified guys into the alliance than just the traditional anchor tenants from EDA.
But none of this comes close to the potential impact of the latest disruptive idea that ESDA is proposing: The founding of a brand new working group that could very well redefine the whole semiconductor supply chain: The ESD Alliance System Scaling Working Group.
Read the rest of Please Crispify: The ESD Alliance System Scaling Working Group
May 12th, 2016 by Peggy Aycinena
IP will be well represented at DAC according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.
Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.
A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]
Read the rest of Mac on DAC: IP is critical, and so is everything else
May 5th, 2016 by Peggy Aycinena
Warren Savage, CEO at IPextreme, is willing to address questions regarding IP content at DAC 2016, enthusiastic in fact. That’s not surprising, given that he serves on the IP Track Committee that reviews the content.
“I think the content’s very good this year,” Savage said in a recent phone call. “We’ve been working on the IP content at the DAC for 3 years, and continue to make progress. I would say the biggest thing [we struggle with] is insufficient time allocated for IP.
“In comparison to previous years, however, the IP and Design tracks have been merged and all put under the same track – something we recommended against, because design-related submissions generally are different from IP-related submissions.”
Read the rest of Warren Savage: Optimism for IP at DAC and beyond
April 20th, 2016 by Peggy Aycinena
The ESD Alliance has announced two additional updates on its remarkable road to renaissance. The Alliance formerly known as the EDA Consortium says Dr. Lucio Lanza, long-time EDA investor and 2014 Kaufman Award winner, is joining the organization’s board of directors, effective immediately.
That news is unique for 4 reasons: a) Lanza is the first new board member since EDAC was relaunched as ESDA; b) Lanza is the only member of the board who is not currently serving as the CEO of a company, the first such circumstance in recent memory; c) Lanza serves on the board of PDF Solutions, triggering another first in that one company is now represented twice on the EDAC/ESDA board with PDF’s John Kibarian also serving therein; and d) Lanza was not elected, but appointed.
Certainly for all of these reasons and more, Dr. Lucio Lanza will serve as a refreshing change agent as the EDA Consortium morphs into the ESD Alliance.
The second major update from the ESD Alliance is the announcement of a “cooperative marketing” partnership with Semico.
Read the rest of ESD Alliance: Lanza and Semico to serve as Change Agents
April 14th, 2016 by Peggy Aycinena
IP now dominates design automation, evidenced in no small measure by ARM’s seat at the head of the table for the ESD Alliance, ESDA being an important sponsor of the Design Automation Conference. Everyone seems to agree that IP reuse is the only way complex mega-systems of the 21st century can be designed, so not surprisingly the DAC program now reflects that reality. There are sessions every day categorized as being IP-related, but are those designations accurate?
I would argue that a lot of the content that’s sitting in the IP Track at DAC is really just about design, and not specifically about IP-based design. To prove that point, below is a complete listing of the sessions in the IP Track that’s set to air between June 6th and 9th at DAC in Austin. Those that are legitimately about IP are bolded, sessions that actually talk about using IP. Those not bolded are ‘just’ about design, or are merely high-level nattering about superficial issues associated with IP reuse.
Conclusion: the number of IP-related sessions are far fewer than one would hope. If IP is this important, why aren’t there more sessions that are really about IP? Is there a conspiracy here?
Fortunately, this next week I’m talking at length with Warren Savage. As CEO of IPextreme, his knowledge about the technology and business of IP is pretty encyclopedic. I will run my conspiracy theory past him: DAC wants you to believe they believe in IP, but in fact the conference is still more about design automation, not about using silicon IP to enhance the process. EDA vendors still rule the roost at DAC.
Read the rest of IP @ DAC: Sound & Fury or Smoke & Mirrors
April 7th, 2016 by Peggy Aycinena
Synopsys Marketing Director and long-time EDA contributor Dave Reed talked recently about the company’s new, highly anticipated product release, Custom Compiler.
“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”
Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”
There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.
“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.
Read the rest of SNPS’ Custom Compiler: closing the FinFET productivity gap