IP Showcase
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Who cares: Cold Fusion vs. 7nm Silicon

 
July 15th, 2015 by Peggy Aycinena

 

Here’s the thing: Yeah, yeah it’s cool that IBM – which apparently invented or first implemented everything [see Below] – has announced 7-nanometer transistors that actually work. Yeah, that’s pretty teeny tiny and everybody’s thrilled. Of course.

Everybody at IBM, GlobalFoundaries, and Samsung (the triumvirate formerly known as Common Platform). Luminaries at Stanford, SUNY, and the Albany NanoTech Complex. Even the Good Governor of the Great Empire State himself.

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Synopsys acquires Elliptic: IP for a Safer World

 
July 2nd, 2015 by Peggy Aycinena

 

Once again it’s an acquisition, and once again the lucky winner’s Synopsys. This time the prize is Elliptic Technologies, “a provider of cryptography cores, security protocol accelerators and processors, Root of Trust embedded security IP modules, secure boot and cryptography middleware, and content protection IP for integration into SoCs. [In other words], security IP cores and software solutions for mobile, automotive, digital home, IoT and cloud computing applications.”

Per the Press Release: “Elliptic’s integrated solutions enable the most efficient silicon design and highest level of security to help prevent a wide range of evolving threats in connected devices such as theft, tampering, side channels attacks, malware and data breaches. As a founding member of the prpl Foundation’s Security Working Group, Elliptic has been dedicated to defining an open security framework for deploying secured and authenticated virtualized services in the IoT and related emerging markets.”

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Sonics: Busy Days, Dark Silicon Knights

 
June 24th, 2015 by Peggy Aycinena

 

These last several months have been busy for Sonics: Release of the latest edition of the company’s “flagship” NoC, SonicsGN 3.0, featuring Sonics’ interleaved multi-channel technology; Release of Version 8.0 of SonicsStudio, the company’s SoC development environment with “improvements for designer productivity and power analysis”; Announcement of Sonics’ ICE-Grain Power Architecture, “a complete power management sub-system comprised of configurable hardware IP blocks, embedded control software, and integrated design tool environment”.

Of the three announcements, the last is the most profound, offering a better, smarter technique for building power management into systems that include Sonics IP. Power is of great concern to anyone working in silicon today, and of even greater concern to those whose business model includes selling both IP and services to the industry.

Drew Wingard, distinguished co-founder & CEO of Sonics, is one of those concerned, articulating the situation in detail on Monday, June 8th, at DAC where he addressed an SRO audience of 150+ technologists anxious to learn more about low power IP. Proving himself one of Sonics’ true Dark Silicon Knights, the following is a snapshot of Wingard’s comments.

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Innovation: Thy name is eSilicon

 
May 25th, 2015 by Peggy Aycinena

 

While news last week out of eSilicon proved again the company’s ability to innovate and build on emerging technologies, a phone call with company VP Mike Gianfagna also proved something: Mike continues to be one of the ablest spokesmen in the industry. Very helpful, because the news is not simple.

On May 19th, the company announced STAR platform, the Self-service, Transparent, Accurate, Real-time platform. Per the press release, “STAR supports eSilicon’s existing IP browsing, instant quoting, and work-in-process tracking capabilities, along with a new chip optimization offering that leverages design virtualization technology. The platform also delivers an enhanced user interface with simplified account setup and access.”

Oh yeah, and the company also announced they’ve unified and re-branded their tools:

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Uniquify & Samsung: Success and mystery abound

 
April 30th, 2015 by Peggy Aycinena

 

It’s the kind of announcement that regularly emanates from IP companies: “Uniquify today announced it developed a DDR3 IP solution for Samsung Electronics’ power-efficient 28nm LPP foundry process that is now in volume production for multiple product lines, including consumer and mobile applications.”

The thing is, there are two bigger take-aways from this announcement than the specifics of the news. One is that news about 28 nanometers is still making news. The way marketing bravado in the industry runs, one would think 10 nanometers is upon us completely.

The other thing is that we’re not talking here about Samsung planning to adopt Uniquify’s DDR3; we’re talking about Samsung using these things in volume production. A very different kettle of fish, and something that IP companies often have so much trouble getting their customers to acknowledge. [Same holds true, of course, for EDA vendors as well.]

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OK, Google: A Man and His Watch

 
April 23rd, 2015 by Peggy Aycinena

 

I’ve got a friend who received an Android Wear (read “watch”) as a gift earlier this year. In the last several months, he’s become addicted to wearing the darn thing although its usefulness is distinctly limited: He can check the time and screen calls without digging a phone out of his pocket. Oh yeah, and when messages and/or emails come in, he knows straightaway.

Other than being a fascinating toy, however, and something to diddle with – particularly for those who like the openness of Android – Wear is really not much more than a distinctive fashion statement and not too much of that.

Nonetheless, now that Apple’s claiming more stupendous success with yet another highly over-hyped product launch (read, “the Apple Watch”), it’s time to re-consider the importance, even gravitas, of this Android Wear thing. After all, let’s not just lay down in the road and let Apple run over us yet again. Let’s cheer on these Android Wear users. Let’s celebrate anybody willing to stand up to the Apple juggernaut. Yay!

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IP @ DAC: Design reuse still not for faint of heart

 
April 16th, 2015 by Peggy Aycinena

 

Building on last year’s success, the 2015 Design Automation Conference in San Francisco is offering even more substantial content in the track centered on silicon IP and design reuse. Reading through the list of topics, speakers, and companies set to be featured across a diverse set of sessions from June 7-9 at Moscone Center, two things are obvious.

One, a lot of work has been done to assemble all of this. And two, it’s possible the thorny issues surrounding IP reuse may never go away: integration, verifying quality, convincing staff to use design blocks that originate outside of the group, and dealing with the massive amounts of data that IP selection and reuse generates.

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DesignWare EV IP: Convolutional Neural Networks at Core of Capabilities

 
April 1st, 2015 by Peggy Aycinena

 

Early Monday morning, Synopsys announced several new bits have been added to their impressive bucket of IP blocks, a new family of DesignWare processors targeted at vision applications. With an honorable pedigree – descent from the ARC technology that came to Synopsys via the 2010 acquisition of Virage Logic – the processors announced on March 30th are designed to be embedded in SoCs, specifically to meet a growing need to digitally “distinguish smiles from frowns, faces from cars, baby carriages from trees or dogs, and even sky from ground.”

These needs were articulated in a March 26th phone call with Synopsys Senior Manager of Product Marketing Mike Thompson, who enthusiastically explained, “The vision market will grow dramatically over the next several years. The next 10-to-15 years will be seen as a paradigm-shift period in how we interact with technology.”

That’s why he’s delighted Synopsys will surpass other players in driving that shift: “There are already a few vision processors available [on the market], and they are largely programmable. We took a slightly different approach, however, with the new DesignWare EV Processors we’ve developed.

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DVCon/SNUG: The Old, Old Story of Design by Committee

 
March 24th, 2015 by Peggy Aycinena

 

We’re only gifted with so many hours of life here on earth, so why would anyone waste them listening to the same lengthy keynote twice in one month? That was the thought that raced through my mind when Synopsys’ Aart de Geus stepped up onto the stage in front of 500+ SNUG attendees at the Santa Clara Convention Center yesterday morning and clicked on his title foil.

“Shift Left,” it said.

“Oh no,” I said. For pity’s sake, this was the exact same talk co-CEO de Geus offered up less than three weeks ago on March 3rd at DVCon in San Jose. I looked around for the nearest exit.

Then, cooler heads prevailed. Mine.

Wait a minute, I said. Three weeks ago I sat in the back of a ballroom at the DoubleTree, listening over the heads of 350 people at DVCon, and typed everything the good doctor said into my tablet, verbatim. I’ve already done the heavy lifting here, I thought. I’ve got his script on my tablet, I’ve seen the slides, and I’ve heard the jokes.

Does Synopsys believe an entirely different audience attends DVCon than that which attends SNUG? Why else would they present the exact same talk at the two venues? Perhaps no one at SNUG actually does verification? Why not compare the SNUG talk to the one at DVCon?

So, with that much entertainment guaranteed I sat back and enjoyed the show.

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Performance, Security, Behavior: how Silicon Cloud’s driving the IoT

 
February 26th, 2015 by Peggy Aycinena

 

In a recent phone call, Silicon Cloud co-founder and CEO, Mojy Chian asserted that the IoT has inspired a new set of initiatives from his lively startup enterprise.

“If you look at the Internet of Things in its entirety, it includes the transmission, aggregation, processing, cloud services and so on.” Chain said, “But it all starts with the nodes, the endpoints, which are the sensors.

“Today we are positioning Silicon Cloud to provide a design-enablement infrastructure for the IoT, a large part of which is the chip design. But now we are extending our services to include design tools for sensors, concentrating on the node itself, and providing a complete infrastructure for node design enablement. We don’t design the semiconductor or the sensor, of course. We provide the design enablement for others to use to design these things.”

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