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Posts Tagged ‘IP’

#54DAC, 1: A Welcome from General Chair Michael ‘Mac’ McNamara

Thursday, October 6th, 2016

I’ve been attending DAC as an exhibitor since 1992, and serving on the executive committee since 2012.  I am thrilled to serve as General Chair for the 54th iteration of this grand conference. (And no it’s not too early to think about DAC; the call for contributions is open now.) Through the years I have seen some big industry changes, most driven by the increasingly powerful tools and automation that this conference has been about — growth that fueled my career, as well!

My first job was as a chip designer at TRW, Sunnyvale back in the 1980s, and we had our own fab in Virginia, and my officemate wrote and maintained our chip design tools, as was pretty typical in those days. I worked at a series of hardware startups after that; and then took all that experience in hand to build better chip design tools. At Chronologic I led the engineering team that built the VCS simulator; then I started Surefire, where we built the SureCov and SureLint verification tools; we merged with Verisity and then into Cadence, where my team developed C-to-Silicon synthesis tools.  If you’re curious, LinkedIn has most of the rest of the story, including the patents I’ve been issued.

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IP Cuts Dynamic Power Dissipation 20% More Than Can Be Achieved With Standard Techniques

Tuesday, January 26th, 2016

CC-100 PowerOp IP 

The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile.  This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.

In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.

The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.

The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF   Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.

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