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Posts Tagged ‘DVCon’

DVCon Europe: European Practicality With International Relevance

Friday, October 30th, 2015

On November 11th and 12th, DVCon Europe will once again take place in the lovely city of Munich. The inaugural event last year demonstrated a clear need for this event in Europe, with a focus on practical information that allowed the attendees to get a rapid, all-encompassing update on a broad range of design and verification techniques. Furthermore, it also showed the international audience those areas where Europe leads, influencing EDA development and thinking on a global basis.

This year’s show promises an even bigger and better program. It is expected to grow significantly, and indeed, early registrations, the size of the exhibit, and the number of papers and tutorials all bear this out. The theme of the conference, focused on the predominantly European automotive semiconductor segment, acts as a driver for next-generation design and verification across the entire industry, given the absolute reliability requirements of these devices. Subject areas, including system-level abstraction, analog/mixed-signal devices, UVM and other advanced verification, will all be discussed during a number of networking opportunities including a Gala dinner, included as part of the registration.

Experience the DVContinuum

Friday, May 15th, 2015

What’s the DVContinuum?

For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November (Munich, Nov 11 – 12, 2015).

For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits. Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.

If you like to share your experience with the DVContinuum, submit your paper: DVCon Europe deadlines are May 11th for your draft paper and June 1st for your Tutorial submission. More info: (India: US: )

The DVContinuum Anno 2015 – a Historic Perspective

As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.


Securing Those Devices

Thursday, January 23rd, 2014

Stories of data hacking have been dominating the news lately.  It seems that hackers are getting smarter and more bold, but what is also making it easier for hackers is that more and more of our everyday devices are connected to the internet making unauthorized access to these devices much easier to achieve and harder to detect.  The Internet of Things is giving rise to a whole new set of security concerns.

As consumers and businesses become more vulnerable to attack, they need to feel more confident that the electronic machines they are using are more secure regardless of the ubiquitous nature of an all-connected world.

In order for providers of these devices to achieve this attack-proof status, they need to invest heavily in design and verification solutions that can secure their hardware designs.  However, this added investment comes at a cost.  That cost is time. We as consumers still want the latest and greatest electronic gadgetry earlier and earlier putting even more pressure on already hyper-stringent time-to-market targets for electronic providers.

Even with these added pressures, current methods for verifying that the hardware can withstand attack are essentially inadequate due to their non-exhaustive nature. Simulation and emulation methods can leave many corner cases left unchecked and thus exposing the hardware to attackers.

This is where formal analysis can come into play.  Formal verification is exhaustive and therefore can find every possible scenario that could leave the hardware device open to hackers.

At DVCon 2014 Jasper technical experts Victor Markus Purri and Lawrence Loh are giving a tutorial on “Formally Verifying Security Aspects of SoC Designs” showing how formal analysis can be applied to this area.

You can register for this tutorial at

You can also download our white paper on Security Path Verification to learn more  –



S2C: FPGA Base prototyping- Download white paper

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