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Posts Tagged ‘concurrent design’

IP Cuts Dynamic Power Dissipation 20% More Than Can Be Achieved With Standard Techniques

Tuesday, January 26th, 2016

CC-100 PowerOp IP 

The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile.  This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.

In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.

The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.

The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF   Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.

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The Concurrent Design-Flow Experiment

Wednesday, August 8th, 2012

At DAC this year I had a lot of fun doing a live experiment to demonstrate some of the benefits and issues with concurrent design flows.  I was at the Cadence Theatre doing a presentation called ‘Controlling the costs of SoC integration‘ and I decided to make the presentation more interactive by creating a design team and seeing some of the effects of getting this team to work concurrently.  We demonstrated how a little ‘twist’ caused a big upset for to team deliveries!

I1

Concurrency

The topic I introduced first was how system design flows are now highly concurrent.  In the production of a system within a very tight timescale, it would be normal to have architecture definition, software development, virtual prototype development, RTL design and verification all happening at the same time, be it IP, sub-system or SoC level design. I represented this as a set of rotating, interacting cogs.

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DownStream: Solutions for Post Processing PCB Designs
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