Chuck Alpert - the General Chair for the 53rd DAC
Chuck is the Group Director for Cadence Digital Signoff Group. Prior to joining Cadence he spent 17 years working at IBM Research in Austin, developing internal EDA tools. He received B.S. and B.A. degrees from Stanford University in 1991 and a Ph.D. in Computer Science from UCLA in 1996.
February 2nd, 2016 by Chuck Alpert - the General Chair for the 53rd DAC
Every year DAC features something new. For the general chair, balancing tried and true conference elements with infusions of change is part of the art of putting on DAC and keeping it fresh. This year one change has to do with art itself — #53DAC features what I believe to be the first art show in the conference’s long history.
No, I’m not asking you to submit that painting you’ve been laboring over, perhaps with the help of last fall’s Bob Ross marathon on Twitch. Rather, this is a call for you to send in the best, most aesthetically interesting images associated with design automation today.
Examples include die photoshots of silicon designs, design floorplans and placemats, 3-D wiring or clock visualizations, lithographic images and thermal maps. But that list is just the starting point. Really, any image associated with how our community is helping to create the world’s astonishing array of electronic devices is welcome.
February 1st, 2016 by Mike Gianfagna
Mike Gianfagna is the VP of marketing at eSilicon Corporation
DAC stands for Design Automation Conference. Everyone: please stop saying “the DAC conference”. This may not be as widespread as folks calling an automated teller machine an ATM machine, but it’s still odd. But I digress…
This year, the 53rd DAC will be held in Austin, Texas starting June 5. I’ve been going to DAC for more years than I will ever put in writing. I’ve seen some marvelous things unveiled at this show. Innovations that impact IC design and manufacturing typically. This year will be different though.
January 26th, 2016 by Michael Hopkins, founder of CurrentRF
CC-100 PowerOp IP
The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile. This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.
In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.
The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.
The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.
January 26th, 2016 by Michael Hopkins, founder of CurrentRF
Most associate USB and it’s hardware as a digital and system data transfer protocol only. Thinking of USB in terms of Analog and RF has only recently been a subject of interest in USB design, a necessity with the advent of USB 3 speeds and protocols. In fact, RF effects become dominant in the data transfer speeds involved with in USB 3. CurrentRF has developed a methodologies and technologies that allow server and network device USB ports, normally thought as digital and system data transfer ports, to be used as Analog/RF pickup ports for system noise and power reduction.
If one opens and ignores the data lines used for any flavor of USB, and focuses only on the resident +5V power and ground lines, one will see a rich source of RF frequencies of significant magnitude, that would enable energy harvesting techniques to be employed to recover this resident, generated energy. In fact, if one utilizes an ac coupled spectrum analyzer of sufficient bandwidth, one will not only see frequency spikes and noise related to USB data transfers, but “coupled in” frequencies and noise energies related to other aspects of servers and network devices.
January 25th, 2016 by Chuck Alpert - the General Chair for the 53rd DAC
Chuck Alpert, General Chair of the 53rd DAC was recently interviewed by Warren Savage on Take Five. Check out what DAC has in store this upcoming June and learn how you can still participate in the DAC program!
October 30th, 2015 by Dave Kelf
On November 11th and 12th, DVCon Europe will once again take place in the lovely city of Munich. The inaugural event last year demonstrated a clear need for this event in Europe, with a focus on practical information that allowed the attendees to get a rapid, all-encompassing update on a broad range of design and verification techniques. Furthermore, it also showed the international audience those areas where Europe leads, influencing EDA development and thinking on a global basis.
This year’s show promises an even bigger and better program. It is expected to grow significantly, and indeed, early registrations, the size of the exhibit, and the number of papers and tutorials all bear this out. The theme of the conference, focused on the predominantly European automotive semiconductor segment, acts as a driver for next-generation design and verification across the entire industry, given the absolute reliability requirements of these devices. Subject areas, including system-level abstraction, analog/mixed-signal devices, UVM and other advanced verification, will all be discussed during a number of networking opportunities including a Gala dinner, included as part of the registration.
May 28th, 2015 by Anne Cirkel
Memorial Day has come and gone, which means two things: summer is here and DAC is officially upon us. In just over a week the doors will open at Moscone Center with a blockbuster designer keynote: Brian Otis, director of Google’s smart contact lens project. Brian, the first Googler to ever take DAC’s main stage, is just one reason to consider registering for the designer and IP tracks if you haven’t already. Others include access to great lineup of marketing-free, engineer-to-engineer sessions, daily networking receptions (yes, you grown-up undergrads, there will be lots of free food and drink), the rest of the keynotes (did you know DAC is also welcoming a MacArthur genius this year?) and of course the exhibit floor. Not bad for just $95.
May 27th, 2015 by Lauro Rizzatti
Emulation is enjoying its moment in the spotlight and none too soon. Design complexity of all types has conspired to make chip verification an arduous task. These days, the fabric of system-on-chip (SoC) designs includes several processing cores, large sets of specialized IP, a plethora of peripherals and complex memories, routinely pushing the design size into the hundreds of million gates. Embedded software now exceeds the complexity of the hardware.
Consider that for each hardware designer there are at least five software developers. No surprise that chip verification and validation has become an overriding concern for all project teams, particularly when hardware and software integration is concerned. Here is where the rubber meets the road, and where the verification challenges reach their peak.
May 15th, 2015 by Oliver Bell
What’s the DVContinuum?
For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November (Munich, Nov 11 – 12, 2015).
For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits. Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.
If you like to share your experience with the DVContinuum, submit your paper: DVCon Europe deadlines are May 11th for your draft paper and June 1st for your Tutorial submission. More info: http://dvcon-europe.org (India: http://dvcon-india.org/ US: http://dvcon.org/ )
The DVContinuum Anno 2015 – a Historic Perspective
As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.
April 22nd, 2015 by Anne Cirkel
Times are good in EDA. 2014 was a record revenue year for our industry, according to an April 13 EDAC announcement. Several technology areas (IC physical design and semiconductor IP) and geographies (the Americas and Asia-Pacific) experienced double digit growth in Q4. The number of people working in EDA is on the rise, too: a total of 31,735 employees at companies EDAC tracks in Q4 2014, compared to 29,880 employees a year earlier. This rising tide is lifting all boats — including #52DAC, which I invite you to register for today if you haven’t already.